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4byte data is not flowing between two modules in verilog

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moro

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Hello all.

i am a bit new in verilog... i have in my top module two other modules instatiated, the problem is when i try to send data from counter to uart, on the logic analyzer connected to uart line, i read 00 00 00 00



The data out/inputs are declared like bellow
Code:
module counter_v2(
                             output reg [31:0] fdata_out 
                           );


module uart4byte(
                           input [31:0] data,
                          );


And in the main module i have the two modules instantiated and tied like bellow,

I tryied some debuging for the uart with parameter zzz[31:0] = 32'h AABBCCDD and this way it works.

But if i try to connect data of the uart4bye with the fdata_out its not working. Why?


Code:
wire stream;

 counter_v2 ccc(
 	.fdata_out(stream)
    );


uart4byte uuu(
  .data(stream),
    );
 
Last edited:

Why are you using a single bit
Code:
wire stream;
to represent a 32-bit connection from fdata_out to data?
 

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