Post place&Route spice simulation problem

Hello all,

I have a digital VLSI design done with Nangate 45nm std cell library with clk frequency 500Mhz. I simulated the gate level netlist after synthesis and everything was fine . Place & route was done in Encounter with no connectivity or geometry violations. I simulated the output verilog netlist from Encounter (after PnR) and also everything was fine. I didn't include SDF timing file since timing is not important for me now I'm just doing logic verification.

Afterwards Spice simulation, so I went to Calibre PEX and specified some nets of interest to have its parasitics extracted (to decrease size of extracted netlist) then I went to HSIM and created a vector file like my testbench in the gate level simulation, BUT the simulation output was zero and many internal nets are having wrong logic. I also didn't attach SDF timing so the only sense of time in my simulations is the delay of gates.

So what might be the problem in HSIM spice simulation ?

I don't know how to start debugging such problem, so I will appreciate any help from experienced people here.

I have some thoughts but I need more experienced people to tell me if this can be the reason for my problem
1) Setup and hold timing violations (but can these violation appear in Spice simulation but not in verilog simulation ?)
2) Can adding the Nangate spice library and transistor model be causing the problem ?
3) problem in Calibre PEX extraction (I don't know how verify this)
4) transistor model

I tried this whole flow with a small design ( 8-bit Counter) with same library files and it works in Spice simulation!

So this should point to a problem in RTL design....BUT how on earth the RTL, gate level netlist and PnR verilog netlist works well but the spice simulation doesn't ??