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  1. #1
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    unable to solve the congestion - design route failing

    Xilinx fpga ultrascale vivado 2016.2

    The design is utilizing 80% of the device and earlier it used to route with =synthesis stratagy - flow alternate routability & congestoion spread logic high for implementation

    now I had to create a small 4 bit counter in the top module and the design is not routing.
    I tried multiple times and the result is same ( although the set up , hold and no. of overlap nodes does change with every run. )

    I cannot reduce the logic anymore, please suggest some way to get a clean bitfile.

    Thanks

    •   Alt13th April 2017, 05:20

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  2. #2
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    Re: unable to solve the congestion - design route failing

    Have you tried playing with your constraints? Tried all the different synthesis and par strategies? What's your speed?



    •   Alt13th April 2017, 06:42

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  3. #3
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    Re: unable to solve the congestion - design route failing

    Hi Barry,

    The speed is 20 MHz
    I have some Multicycle path constraints. Do you mean area constraints? I havn't put any area constraints.
    Will try all synthesis and par strategies . Thanks.



    •   Alt13th April 2017, 07:36

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  4. #4
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    Re: unable to solve the congestion - design route failing

    20mhz? And you're struggling to route in an ultras ale? This suggests you have done really long and large combinatorial paths. It sounds like you really need to pipeline your design.



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    Re: unable to solve the congestion - design route failing

    @Tricky,
    I Agree, loo much combinatorial, as the rtl was meant for ASIC . cant do much on that front. I mean cant pipeline.
    Also the device utilization has gone up to 82% on this Stacked silicon device



    •   Alt13th April 2017, 08:43

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  6. #6
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    Re: unable to solve the congestion - design route failing

    Have you many wide/long buses within the design? If it is only 20MHz maybe you can replace a parallel bus with a serial one? I haven't had to resort to this in my designs (yet), but this general concept may be of some use:
    http://electronicdesign.com/eda/usin...e-fpga-routing



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