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    Altera Cyclone II mini

    I have a Cyclone II mini development board and I saw a tutorial on youtube on how to use it. Thing that I don't understand is how to do pin assignments. For example, there are 3 LEDs (attached picture) and I don't know which pins are connected to those LEDs. I didn't fins such things on the web. The official Altera board for Cyclone is DE2 (or DE1).

    Any idea about that?

    •   Alt12th April 2017, 15:12

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    Re: Altera Cyclone II mini

    The board has FPGA pin numbers printed on the PCB, you can download the EP2C5 pinout file from Altera web site and select the pins for your applications or assign the pins directly in Quartus Pin Planner Tools.

    Regarding LED connections, it took me 5 clicks to locate the Mini Board schematic on the internet, the LEDs are connected to pin 3, 7 and 9. https://www.openimpulse.com/blog/pro...category/ep2c5


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    Re: Altera Cyclone II mini

    Thanks for the quick reply. I got it. In fact, I didn't noticed the LED symbols in the schematic file.
    One more question.... This board only have 3 LEDs. How can I see the result of the computation. For example, I want to implement an 8-bit counter and see the result 1, 2, ..., 255. Or I want to see the result of multiplying two numbers. Is it possible to view the output on the Quartus console?



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    Re: Altera Cyclone II mini

    For example, I want to implement an 8-bit counter and see the result 1, 2, ..., 255.
    This board is small and so has limitations. So you either need additional h/w attachments or work-arounds.

    For eg, when your counter reaches a value of 255 then drive a signal HIGH so that it will light up one on-board LED. You can devise more such tricks!
    .....yes, I do this for fun!



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    Re: Altera Cyclone II mini

    So that means very very limited board!
    I was thinking about sending/receiving data through JTAG or AS ports. For example, sending a 32 bit data and receiving its checksum. Is that possible?

    One more question. As I powered on the board and connected the blaster to the computer via USB port. As you can see in the picture, the blaster is powered on, but the programmer's menu shows no hardware. Any idea about that?

    - - - Updated - - -

    It seems that it is a driver issue. I am using windows 10 and the Quartus is 7. Is that OK?



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    Re: Altera Cyclone II mini

    Quartus II version 7 only works with XP or 2000 it is at least 9 generations of the tool back. Quartus II is currently at 16.1, and should work on Windows 10.

    I'm pretty sure there is no support for XP programs on Win10 unless you run a virtual XP machine under win10.



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    Re: Altera Cyclone II mini

    I'm presently using Quartus 9 on Windows 7 to maintain Cyclone and Cyclone II designs. Not sure if it runs on Windows 10, but not impossible.

    Except for some PLL restrictions and the relative low logic element count, EP2C5 isn't too different from recent FPGA.



    •   Alt12th April 2017, 17:10

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    Re: Altera Cyclone II mini

    Quote Originally Posted by FvM View Post
    I'm presently using Quartus 9 on Windows 7 to maintain Cyclone and Cyclone II designs. Not sure if it runs on Windows 10, but not impossible.
    In this case we are talking about a WinXP program being run on Win7....I've tried running WinXP programs on Win7 and now Win10 and it's hit or miss. Usually you end up having to run the program under a virtual machine.



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    Re: Altera Cyclone II mini

    I remember that I had problem with installing the device on quartus 13 (the latest version that supports cyclone II) on windows 10. The problem was that it said can not qdz file although the path and the file were valid.
    So, I downloaded an older version. I will test with v10.


    So that means very very limited board!
    I was thinking about sending/receiving data through JTAG or AS ports. For example, sending a 32 bit data and receiving its checksum. Is that possible?
    Any suggestion for that? If the capability is limited to one push button and 3 LEDs, then why using a 60K logic elements and a 114 pin chip?!



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    Re: Altera Cyclone II mini

    Try some of the stuff here before uninstalling and reinstalling the huge installations of QuartusII.

    https://www.howtogeek.com/228689/how...on-windows-10/


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    Re: Altera Cyclone II mini

    Any suggestion for that? If the capability is limited to one push button and 3 LEDs, then why using a 60K logic elements and a 114 pin chip?!
    Have you seen the rows of parallel pins surrounding the FPGA? If, yes have you consulted the board development guide as to how can you use them?
    .....yes, I do this for fun!


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    Re: Altera Cyclone II mini

    Quote Originally Posted by ads-ee View Post
    Try some of the stuff here before uninstalling and reinstalling the huge installations of QuartusII.

    https://www.howtogeek.com/228689/how...on-windows-10/
    OK. That was good. I restarted the windows 10 in the test mode as explained in that page and then installed the blaster driver. The driver files are located in quartus\driver folder. Now it works.



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    Re: Altera Cyclone II mini

    Quote Originally Posted by dpaul View Post
    Have you seen the rows of parallel pins surrounding the FPGA? If, yes have you consulted the board development guide as to how can you use them?
    I know that I have to put some seven segments or LCD on the bread board and connect them to the IO pins. However, I was thinking on how to send/receive data to/from computer. For example, setting A and B as two floating point numbers in the VHDL code and then get the multiplication and display on the monitor. Is that possible with this board? If you know any guide, please let me know.



    •   Alt13th April 2017, 12:35

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    Re: Altera Cyclone II mini

    However, I was thinking on how to send/receive data to/from computer. For example, setting A and B as two floating point numbers in the VHDL code and then get the multiplication and display on the monitor. Is that possible with this board? If you know any guide, please let me know.
    In my opinion serial interface would be the simplest (keeping the tx and rx pins separate).
    All you need is an UART on your FPGA and for your PC an USB port with cable will suffice.
    .....yes, I do this for fun!



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    Re: Altera Cyclone II mini

    I actually consider the lack of additional devices on the board an advantage, not a deficiency. You do have all the pins available and no unnecessary components you don't use as with typical evaluation boards.
    Get some USB<->3.3V serial converter (very cheap on eBay) and implement a simple UART on the FPGA. This will way you will have a very cheap and versatile way to let the FPGA communicate to the outside world (your PC) on only two pins.

    I have the following config running well on the exact same board on my desk.

    Code:
    library ieee;
        use ieee.std_logic_1164.all;
        use ieee.numeric_std.all;
    
    entity uart is
        generic
        (
            clk_freq  : integer   := 50000000; -- hertz
            baudrate  : integer   := 460800     -- bits/s
        ); 
        port
        (
            rxd      : in   std_logic;
            rx_data  : out  std_logic_vector(7 downto 0);
            rx_busy  : out  std_logic;
            txd      : out  std_logic;
            tx_data  : in   std_logic_vector(7 downto 0);
            tx_start : in   std_logic;
            tx_busy  : out  std_logic;
            clk      : in   std_logic
         );
    end uart;
    
    architecture rtl of uart is
        signal txstart  : std_logic := '0';
        signal txsr     : std_logic_vector  (9 downto 0) := (others => '1');  -- start bit, 8 data bits,
        signal txbitcnt : integer range 0 to 10 := 10;
        signal txcnt    : integer range 0 to (clk_freq / baudrate) - 1;
    
        signal rxd_sr   : std_logic_vector(3 downto 0) := (others => '1');     -- edge detection and synchronization
        signal rxsr     : std_logic_vector(7 downto 0) := (others => '0');     -- 8 data bits
        signal rxbitcnt : integer range 0 to 9 := 9;
        signal rxcnt    : integer range 0 to (clk_freq / baudrate) - 1; 
    
    begin
        -- send
        p_send : process 
        begin
            wait until rising_edge(clk);
            txstart <= tx_start;
            if (tx_start = '1' and txstart = '0') then  -- rising edge, start
                txcnt    <= 0;                          -- init counter
                txbitcnt <= 0;                      
                txsr     <= '1' & tx_data & '0';        -- stop bit, 8 data bits, start bit, start rightmost
            else
                if txcnt < (clk_freq / baudrate) - 1 then
                    txcnt <= txcnt + 1;
                else                                    -- output next bit  
                    if txbitcnt < 10 then
                        txcnt    <= 0;
                        txbitcnt <= txbitcnt + 1;
                        txsr     <= '1' & txsr(txsr'left downto 1);
                    end if;
                end if;
            end if;
        end process p_send;
        txd     <= txsr(0);  -- LSB first
        tx_busy <= '1' when tx_start = '1' or txbitcnt < 10 else '0';
       
        -- receive
        p_receive : process begin
            wait until rising_edge(clk);
            rxd_sr <= rxd_sr(rxd_sr'left - 1 downto 0) & rxd;
            if rxbitcnt < 9 then                                    -- receiving
                if rxcnt < (clk_freq / baudrate) - 1 then 
                    rxcnt    <= rxcnt + 1;
                else
                    rxcnt    <= 0; 
                    rxbitcnt <= rxbitcnt + 1;
                    rxsr     <= rxd_sr(rxd_sr'left - 1) & rxsr(rxsr'left downto 1); -- shift right, LSB first
                end if;
            else                                                    -- wait for start bit
                if rxd_sr(3 downto 2) = "10" then                   -- falling edge of start bit
                    rxcnt    <= ((clk_freq / baudrate) - 1) / 2;    -- wait for half of bit time
                    rxbitcnt <= 0;
                end if;
            end if;
        end process p_receive;
        rx_data <= rxsr;
        rx_busy <= '1' when rxbitcnt < 9 else '0';
    end architecture rtl;



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