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    Changing the function of logic blocks in Xilinx FPGA

    Hi,
    Is there a way to change the logical function of the elements in FPGA by modifying the libraries or something like that?
    Assume that we have a design that implementation of this design on FPGA contains on or more AND gates. Now we want to do something that this AND, works as an OR gate by not modifying the design. In other words, we want to force FPGA elements to malfunction.
    Is it possible to do such thing?

    Thanks

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    Re: Changing the function of logic blocks in Xilinx FPGA

    What?

    You want to change the function by not changing the function? You want to change the libraries but not have it change your design? You want to force the FPGA to malfunction? You could lower the voltage. You could expose it to radiation.

    This really all doesn't make much sense, at least to me.



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    Re: Changing the function of logic blocks in Xilinx FPGA

    The simple answer is yes you could, if you replace one set of your code with another set of your code that is pin compatible. You cannot change the base primitives.



    •   Alt12th April 2017, 18:55

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    Re: Changing the function of logic blocks in Xilinx FPGA

    Quote Originally Posted by TrickyDicky View Post
    You cannot change the base primitives.
    If you somehow managed to do so, then the tools would probably not work correctly anymore. As anywhere it needs to implement an AND gate you would end up with an OR gate instead, even in places where you don't want to do that.

    The closest to what you are attempting to do is to write out an EDIF netlist and modify the nestlist to change a cell from one type to another to create your "FPGA malfunction".

    Not sure what you are trying to do here, but it seems like a ridiculous idea.



    •   Alt12th April 2017, 19:22

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    Re: Changing the function of logic blocks in Xilinx FPGA

    The whole idea of changing an AND to an OR IS CHANGING THE DESIGN. There are no AND or OR gates in the FPGA, there are LUTs (lookup tables) that implement the logic function.



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    Re: Changing the function of logic blocks in Xilinx FPGA

    This sounds like partial reconfiguration. Many devices support this, but tool support may be difficult to get.



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    Re: Changing the function of logic blocks in Xilinx FPGA

    Quote Originally Posted by barry View Post
    There are no AND or OR gates in the FPGA, there are LUTs (lookup tables) that implement the logic function.
    I know that. That was just an example, I mean that for example a LUT was supposed to provide outputs as AND gate, and now instead of AND output, we want it to generate other outputs, no matter what.
    But, as I said before, we dont want to change the design or any modification before the synthesis process.



    •   Alt13th April 2017, 08:15

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    Re: Changing the function of logic blocks in Xilinx FPGA

    Quote Originally Posted by barry View Post
    What?

    You want to force the FPGA to malfunction? You could lower the voltage. You could expose it to radiation.

    This really all doesn't make much sense, at least to me.
    The idea is complicated somehow, but the point is, by lowering the voltage or exposing it to radiation, the malfunction effects will become uncontrollable and I can not observe the changes.

    - - - Updated - - -

    Quote Originally Posted by ads-ee View Post

    The closest to what you are attempting to do is to write out an EDIF netlist and modify the nestlist to change a cell from one type to another to create your "FPGA malfunction".
    By changing the netlist, you just change what you wanted the FPGA to do. And the FPGA is working just as well as before! by FPGA malfunction, I mean that you loaded the FPGA with X design, but it doesn't works as X.

    Look at the image below:
    Click image for larger version. 

Name:	Capture.JPG 
Views:	2 
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ID:	137840

    I want to change the behavior of this logic block. But I don't know how. What if I target the flip-flop. Is it possible?



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    Re: Changing the function of logic blocks in Xilinx FPGA

    A tool might give you the option to change LUT vectors or logic cell options and save the changes to the configuration bitstream without synthesizing and fitting the design anew. Don't know if it's possible with recent Xilinx tools.

    Altera Quartus has the Resource Property Editor for this purpose.


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    Re: Changing the function of logic blocks in Xilinx FPGA

    Quote Originally Posted by FvM View Post
    A tool might give you the option to change LUT vectors or logic cell options and save the changes to the configuration bitstream without synthesizing and fitting the design anew. Don't know if it's possible with recent Xilinx tools.

    Altera Quartus has the Resource Property Editor for this purpose.
    Thanks for your answer dear FvM.
    This Property Editor is something like FPGA Editor provided by Xilinx? You mentioned that this tool is capable of changing logic cell options. Do these options include logical behavior of the cell or only the connection and interconnection changes ?



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    Re: Changing the function of logic blocks in Xilinx FPGA

    As said, I was talking about the Altera tool, don't know regarding Xilinx. LUT vector defines the logic function, it can e.g. flip AND to OR.

    In practice, there are very little applications for this kind of engineering change in regular design flow. What I did, is e.g. modifying PLL phase shifts or output driver parameters without recompilation.


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    •   Alt13th April 2017, 11:49

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    Re: Changing the function of logic blocks in Xilinx FPGA

    Xilinx used to have FPGA Editor (I don't know if they still have it). It would allow you to go in and change routing and, I believe, LUT functions and then generate a bit file. But I still have no idea why you would want to do this.



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    Re: Changing the function of logic blocks in Xilinx FPGA

    Vivado has an editor and you can modify the LUT and write out a bitstream if you so desire. Though I really don't understand why they want to do this.



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    Re: Changing the function of logic blocks in Xilinx FPGA

    Quote Originally Posted by barry View Post
    But I still have no idea why you would want to do this.
    Its kind of testing the design against unwanted condition in working situation.



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    Re: Changing the function of logic blocks in Xilinx FPGA

    Quote Originally Posted by ads-ee View Post
    Vivado has an editor and you can modify the LUT and write out a bitstream if you so desire. Though I really don't understand why they want to do this.
    You mean modifying the generated bitstream before downloading to FPGA? If so, does it need to be re-synthesized?



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