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parallel interface for data transferring

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viyaaloth

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Dear All,

Could you please suggest some simple parallel interfaces that can be used for data transfer between two inter IP with in FPGA (in terms of hardware design).


Regards,
Viya
 

Hi,
You could try:
- AXI-lite
- Wishbone
- Avalon
Kris
 

AXI-S is better if you know that you will have a continuous steam of data which has a valid end (tlast signal).
If not satisfied with AXI-S, then build your own. All you need to do is to implement the concept of handshaking.

On the rising edge of the system clock, your device(Tx) will inform the other device(Rx) that it has data to send. So you just make a signal HIGH. The other device(Rx) will sample this signal and if HIGH, should send out another reply-signal driving it HIGH to indicate that it can accept the data. If the other device(Rx) cannot accept the data then let this reply-signal remain LOW. Now if the data sending device(Tx) samples this reply-signal as HIGH, just make your data available on the data bus on the next clock cycle.

You are the architect, so you need to compare all available protocol and decide what suites best for your design!
 
Hi Dpaul,

Thanks for your suggestion. If i am trying to build my own parallel interface, what are all the things that i need to concentrate. I used only available standard interfaces. while creating my own interface, whether it is needed to compliant to any standard protocol available in industry.


Regards,
viyaaloth
 

Hi,

* n data lines (as much as you need)
* one strobe signal to identify that the databits are valid
(the strobe signal should show "invalid" when new data is appied until the data is considered as stable. It needs to toggle even if you send the same data value than before.)

Klaus
 

while creating my own interface, whether it is needed to compliant to any standard protocol available in industry.
For intra-chip communication, you need not explain to your client what data transfer protocol is being followed (keep the protocol as an internal documentation).
If you can transfer your desired data volume within the desired number of clock cycles, you are good to go.
 

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