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    How to test different values of generic (generic map) in vhdl all in one testbench -

    Hi

    VHDL-I was wondering how to test different values/conditions of generics (generic map) all in one testbench without making multiple testbenches with different generic conditions...


    Thanks a lot

    •   Alt11th April 2017, 21:38

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    Re: How to test different values of generic (generic map) in vhdl all in one testben

    How about a package file that has a bunch of constant declarations that you use for the generic map constants you assign.



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    Re: How to test different values of generic (generic map) in vhdl all in one testben

    Your testbenches can also have generics. In modelsim, you can pass generics using -g. This only works for basic types.
    Code:
    vsim -gANY_NAME_HERE=5
    There are other options as well. For example, within a function in a package you can convert a test case number into a more complex type. I think you can also have functions that read complex test cases from a file as well.



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    Re: How to test different values of generic (generic map) in vhdl all in one testben

    You can't change generics during run time, so the only options are to either
    1) run the test bench multiple times using scripting
    2) instantiate the dut multiple times in a single testbench.

    Usually, people use the first method to keep single cases separate and allow easier debugging



    •   Alt12th April 2017, 07:43

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    Re: How to test different values of generic (generic map) in vhdl all in one testben

    Thanks everyone. I was wondering if anyone can share an example here passing on generics with are std_logic_vectors. Also then how to use assert statements then as it will be different for different generic parameters.



    •   Alt12th April 2017, 11:10

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    Re: How to test different values of generic (generic map) in vhdl all in one testben

    I tried passing it but it didn't work for me. A working example will be appreciated.Thanks



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    Re: How to test different values of generic (generic map) in vhdl all in one testben

    An example would be rather simple as ant generics are possible. Are you asking for code examples or scripting examples?

    It may me easier if you post the code that isn't working so we can see why.



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    Re: How to test different values of generic (generic map) in vhdl all in one testben

    Quote Originally Posted by TrickyDicky View Post
    An example would be rather simple as ant generics are possible. Are you asking for code examples or scripting examples?

    It may me easier if you post the code that isn't working so we can see why.
    Both would be nice.Thanks very much



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    Re: How to test different values of generic (generic map) in vhdl all in one testben

    For generics

    Code VHDL - [expand]
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    Library IEEE;
    Use IEEE.std_logic_1164.all;
     
    Entity mytest is
      Generic (
        Myslv : std_logic_vector
      )
    End entity mytest;
     
    Architecture test of mytest is
    Begin
     
      Inst : entity work.myent
      Generic map (
        Some_generic => myslv
      )
    End architecture;

    Code:
    Vsim mytest -gmyslv=11001100



    •   Alt13th April 2017, 19:22

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    Re: How to test different values of generic (generic map) in vhdl all in one testben

    Quote Originally Posted by TrickyDicky View Post
    For generics

    Code VHDL - [expand]
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    Library IEEE;
    Use IEEE.std_logic_1164.all;
     
    Entity mytest is
      Generic (
        Myslv : std_logic_vector
      )
    End entity mytest;
     
    Architecture test of mytest is
    Begin
     
      Inst : entity work.myent
      Generic map (
        Some_generic => myslv
      )
    End architecture;

    Code:
    Vsim mytest -gmyslv=11001100
    Thanks very much. I did exactly the same but was not able to make it work. Anyway you very also suggesting that one can use the functions to chane the generics many time in a single test bench. Can I have an example for that? Cheers



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    Re: How to test different values of generic (generic map) in vhdl all in one testben

    Quote Originally Posted by sonika111 View Post
    Thanks very much. I did exactly the same but was not able to make it work. Anyway you very also suggesting that one can use the functions to chane the generics many time in a single test bench. Can I have an example for that? Cheers
    You must start the simulator once for every combination of generics, but you can supply them from the command line so the design and test bench files can stay unchanged.



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