to realize low pulse duration using Inverter and XOR gate in FPGA

Hi, for testing another circuit, I have to generate pulse with 1ns pulse width.
My basic idea is to input 2 signals into Xor gate. one is origin signal and another is delayed signal. I think the delay can be realized by several inverters.
I use Spartan 3E which has 50Mhz internal clk source. Also, I do this FPGA design in schematic level.

However, the simulation shows the signal is not delayed and the output is not what I desired.

Does this solution work?

There is no way to guarantee the pulse is 1 ns as the timing of an FPGA has a minimum and maximum range of values depending on process voltage and temperature. Using inverters will guarantee a extremely wide range of pulse width as the LUTs have wide timing variation across PVT.

About the only way you could conceivably attempt to do this is by using the clock and a DCM to delay a second clock by 1 ns (not even sure the Spartan 3E has the resolution to do this). Then use the two clocks to generate signals out of FFs that you then XOR together to make the pulse. Placement and outing of this circuit becomes critical as any difference in the delay between the two FFs and the XOR gate use to combine the outputs will affect the pulse width.

19910219 said:

Hi, for testing another circuit, I have to generate pulse with 1ns pulse width.
My basic idea is to input 2 signals into Xor gate. one is origin signal and another is delayed signal. I think the delay can be realized by several inverters.
I use Spartan 3E which has 50Mhz internal clk source. Also, I do this FPGA design in schematic level.

However, the simulation shows the signal is not delayed and the output is not what I desired.

Does this solution work?

Click to expand...

FPGA is a terrible platform for achieving what you want. Have you considered a discrete PLL/clock generator?

Yes, That's a good way.
However, a new problem's coming. Could you give me some hint for solving it?
I tried to use FPGA to generate a pulse as an input to a PCB design. The design is an amplifier using BJT transistor.
But less than 0.7 V pulse can be transmitted to the board. How can I amplify the pulse generated from FPGA?
I need a pulse with amplitude which is more than 1.2 V.

do you know what a level shifter is?

ThisIsNotSam said:

do you know what a level shifter is?

Click to expand...

yes，but based on my knowledge, it's a on chip design. I'm unable to do in this way..

What circuit are you testing out of curiosity?

My basic idea is to input 2 signals into Xor gate. one is origin signal and another is delayed signal. I think the delay can be realized by several inverters.
I use Spartan 3E which has 50Mhz internal clk source. Also, I do this FPGA design in schematic level.

Click to expand...

Just entering the imagined logic in HDL or schematic design doesn't work because the synthesis tool removes the logically redundant gates. You need to tell the tool explicitly to keep it, using synthesis directives or low level primitives. I'm not familiar with the Xilinx tool chain, but you surely find the answer in documentation or Xilinx forum.

Generating the intended pulse shape with gate delays may be difficult though, but you should see it working in principle.

Referring to analog signal processing means, we would use a shorted delay line to generate a ns pulse form a rising edge.