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On-chip Loop filter Capacitor and Power line across it

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NovelPanda

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Dear All:

I need to integrate an on-chip capacitor (~40pF) in the loop filter and it is a MOM cap consisting of M1-M8. To fully utilize the area, I want to place the power lines on top of the capacitor by using thick copper and Aluminium M9-M11. The power line serve as VDD and GND only for analog circuits. Has someone done this before and what could be the potential problems? Or it is acceptable?

Thanks in advance!
 

40 pF is quite large, as I understood you want to use M1 and M8 as electrodes with oxide in between?!. I don't know your technology but maybe there is a quite big distance between M1 and M8 which would further increase your area usage. If you know your area of capacitor and the area of your power grid, you can roughly calculate your coupling capacitance. If it's a problem is hard to answer, it depends on your analog circuitry (frequency etc.), second it depends on the signal of the capacitor, because this can also couple into your vcc or gnd grid, depending on your layout. You see the question is not easy to answer, maybe tell more about what you want to do.
 

If the filter cap is shunt-to-ground, then more ground above
it would be a don't-care. If both ends are active then I'd be
sure that the driven end is the top plate (but then you have
the receiving end losing charge to substrate parasitic caps).

I'd assume you mean a sandwich cap of m1, m2, m3, m4, m5,
m6, m7, m8 to get that capacitance.

Could use m9 as a driven guard plate perhaps, locally, with
small impact to the end-to-end bus resistance (use m9 for
most of the distance except over the cap).
 

Thanks johnjoe and freebirf. I implement the big cap. by MOM from M1-M8 (it is a finger capacitor not sandwich, each finger will only have 100 nm width, and the capacitance is mostly coming from the coupling between metal fingers rather than from the oxide between different metal layers). The cap. serves as the largest capacitor in the loop filter of a PLL. One end of cap. is connected to Vctrl and the other end tied to GND. So the ground planes implemented by M9-M11 above the cap. should be dont-care? I am using 40nm CMOS.
 

Yes, a don't-care / bonus / slight parasitics adder to
the designed MOM value. Might have to shave the
cap property some to get the right answer post-
layout-extracted (if more is not entirely better).
 

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