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Conventional charge redistribution dac

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niloufar-navidi

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Hi
I cannot understand why in the comparison of the second MSB, Input voltage to the comparator would be :
for1.JPG
msb2-1.JPG
While the charge on MSB has been discharged and there should be no Vref/2 anymore.
And vise versa , When MSB has not been discharged the input voltage to the comparator is:
for2.JPG
cha.JPG
While there should be a vref/2 in this formula.

The complete instruction: **broken link removed**

- - - Updated - - -

I think TI manual has got some problems, When MSB is 1 (bit4 here) and we are going to decide MSB/2, MSB cap should remain connected to vref!
 
Last edited:

Sorry, I don't understand, Is that Q1=Q2? Because I do understand that, But the manual is some how troubled, If you take a look Equations written in
the pictures do not match the situation of bit cycle. I have checked it with these articles too:

"All-MOS Charge Redistribution Analog-to-Digital Conversion Techniques—Part I"
JAMES L. McCREARY, STUDENT MEMBER, IEEE, AND PAUL R. GRAY, MEMBER, IEEE

"An Energy-Efficient Charge Recycling Approach for a SAR Converter With Capacitive DAC"
Brian P. Ginsburg and Anantha P. Chandrakasan
 

erikl said:
Code: 
v1:v2 = c2:c1
Click to expand...
This means: voltage division ratio is inversely proportional to the capacitance ratio.

niloufar-navidi said:
I cannot understand why in the comparison of the second MSB, Input voltage to the comparator would be :
View attachment 137801
View attachment 137800
While the charge on MSB has been discharged and there should be no Vref/2 anymore.
And vise versa , When MSB has not been discharged the input voltage to the comparator is:
View attachment 137802
View attachment 137803
While there should be a vref/2 in this formula.
Click to expand...

You have to think in terms of charge carrier distribution and that the inverting input of an opAmp is virtually held at the same potential as the non-inverting input (GND in this case).

niloufar-navidi said:
I think TI manual has got some problems ...
Click to expand...
I think the bottom equation in this snippet of the TI paper is not correct:

Instead, it should say
Vc = -Vin + (bit 4 * Vref/2) + Vref/4
Click to expand...
 

I know charge conservation (Q1=Q2 or C1.V1=C2.V2), It is the most basic equation we should know to analyze charge redistribution or circuits involving capacitors, I am saying that I think it is not used properly, I have edited it like below:
nil11.JPG
nil22.JPG
 

Why certainly! You exchanged the opAmp's input polarities! Same correctness as before.
 

in TI Manual we have this:
nil33.JPG
so for the configuration below I write:
nil44.JPG
V1*3C/2=V2*C/2
and V1+ V2 = Vref
so : V1= Vref/4 and V2=3Vref/4
so I think according to grounding the MSB we should write the out pot coltage like this: Vc=-Vin+Vref/4
but sounds that TI Manual has added Vref/2 from previous complarison to the equation : Vc=-Vin+Vref/2+Vref/4=-Vin+3Vref/4
It is in contrast with grounding the MSB cap and disharging it from previous charge :
nil55.JPG
 

Re: Conventional charge redistribution ADC

niloufar-navidi said:
... so for the configuration below I write:
View attachment 138034
V1*3C/2=V2*C/2
and V1+ V2 = Vref
so : V1= Vref/4 and V2=3Vref/4
Click to expand...
This is correct, as long as you neglect the fact, that "the MSB"'s upper terminal has (simultaneously) been connected to GND.

niloufar-navidi said:
so I think according to grounding the MSB we should write the out pot coltage like this: Vc=-Vin+Vref/4
but sounds that TI Manual has added Vref/2 from previous complarison to the equation : Vc=-Vin+Vref/2+Vref/4=-Vin+3Vref/4
It is in contrast with grounding the MSB cap and disharging it from previous charge :
Click to expand...

But now consider the fact, that "the MSB" cap's upper terminal has been connected to GND : This cap C still contains the charge Q = C * (Vref/2), which now is added to the charge at the node Vc , by this adding another Vref/2 to this node:

I guess that's why this ADC (not a DAC - as in your title) is called a charge redistribution SAR-ADC .
 
Re: Conventional charge redistribution ADC

I really don't know ,since these equations are written in the steady state and in the manual it is written that C is discharged when s4 is connected to ground:
nil66.JPG
 

Re: Conventional charge redistribution ADC

May be this is an unfortunate diction, however I think it should mean: discharge the charge stored in capacitor C (Q=C*Vref/2) - before connected between the nodes Vref(+) and Vc(-) - after switching between nodes Vc(+) and GND(-). This transfers a charge Qref=C*Vref of opposite polarity to the node Vc, which changes its original (part) charge Cbefore=C*-Vref/2 (related to GND) into Cafter=C*Vref/2 - without regard to the charges already present (due to -Vin and Vref/4 , in this case).
 

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