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Amplifier Layout Question

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Please dont feed any AC to the input. Just short the input to a proper DC value and measure the output by the spectrum analyzer. If you can see a spectrum at 140kHz without any AC input, then your chip is oscillating at this frequency. Normally when the chip oscillates, you can always observe harmonics rather than sub-harmonics.

I could not find any spectrum analyzer to test. But when frequency changes (100kHz - 200Khz) all harmonics and sub harmonics are changing and the result is the same. I think it is not related directly with 140Khz, it is related with AC Input frequency, but how?

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I wonder if the in- and output "detour" traces might cause problems due to parasitic coupling? They seem technically useless regarding the amplifier frequency range.

But I rather expect a problem a defect output transformer (e.g. with winding short). I presume, the transformer parameters can be verified in circuit with a suitable LCR meter. Or any other component defect.

We have tired different transformer and same transformer with different channels. Also tried to change primary inductance but no improvement. Other channles also have detour traces.

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How many parts (PCBs) did you test?

3, but all are the same manufacturing party.

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I would add a cap from pin 6 to pin 2 of the op amp. 10pf or so

We have tried that option, but no improvement.

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What is coming in on that big connector, which the
problem channel "just happens" to be butted up
against? Do traces from the connector run below
the problem channel's more sensitive bits?

Sorry, but I could not understand exactly what you mean:(
 

I have marked up your layout to make this clearer


Victim has all connections just inside the marked area, only input and output connected to connector. Some other channels input and output goes under this area in different planes. But we are tried to assembly just only this channel but nothing changed.

I am suspicious about any manufacturing problem, but I do not know how can I check it. I have asked the manufacturer and waiting.
 

We have solved the oscillation problem. The reason was "Ferroresonance" related with low output capacitance. When we changed 220nF to 10uF and add serial 5 ohm resistance oscillation has gone. But the problematic channel still insists on low gain, now it is not oscillates but distorts. I am suspicious about layout but, I could not figure out how.

Please find Analog Inputs, Transformer Outputs and Opamp -IN and OUT connections below. Transfomer OUT goes under the OUT pin of opamp but differen layer, is it problem? What measures should we take for opamp layout?
Green traces-Analog Inputs
Light Blue traces-Transformer outputs
Yellow Rectangle-Problematic Channel

Also you can find distorted signal as attached.
 

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I might suggest a layer-by-layer XOR of the bad
channel vs the good. Do not know whether PCB
DRC tools can do this but it's a common debug /
verification thing to do in IC layouts. If possible
use a "blowback" database from the PCB mfr.
This could turn up some routing difference -
either intentional (which would be in your DB)
or accidental (spot on PCB house photomask
becomes via / line break.

For that matter an X-ray inspection facility
could produce you an all-layers image which
I'd bet someone could do a pattern recognition
difference on - maybe a MIL grade PCB outfit
or one that does any aerospace grade work,
would either already have this in house or
tell you who they use.

I do notice offhand that the problem channel,
unlike the rest, has its cyan trace (function = ?)
making a 3/4 loop over its own circuitry - the
others are more straight and more random.
Maybe this is your "magnetic pickup". Might
cut and peel (if you're lucky enough that cyan
is a topside or bottom side layer) and mag-wire
direct, see what changes. If not, maybe find a
lucky drill-point that takes out only that trace.

Although the two on the left are kinda weird
loop antennas too... kooky routing, why the
matchy-matchy line lengths (only reason that
comes to mind) for sub-MHz stuff when it's
1nS/foot? The bad boy, though, has the largest
loop area.

Any chance that the problem is documentary -
like the component install drawing or silkscreen
has an electrolytic cap or a diode reverse-placed?
 

1. Checking parasitic capacitances is (theoretically) straightforward - if you do RC (or C only) extraction of the PCB layout, it is easy to check parasitic coupling capacitances between victims and aggressors - and hence see if you have any outliers for the problematic channel. Can you do C or RC extraction of this PCB?

2. Input and output loops for the problematic channel look large, and located side-by-side to each other - meaning there may be large inductive coupling between them. Can you manually add inductive coupling in your simulation and see if the results resemble measurements?

3. You didn't show the GNDA layout - if it is different for the problematic channel than other channels - maybe you have ground bounce problem (combined with inductive loop coupling or self inductance?).
 

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