Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

DRC warning of cadence

Status
Not open for further replies.

m_kuty

Member level 2
Joined
Mar 2, 2015
Messages
46
Helped
1
Reputation
2
Reaction score
1
Trophy points
8
Activity points
333
Hello everyone

I Need your help with my opamp design particularly with DRC and I have got this warning

ERC Warning: Latchup rule LAT3 distance s/d diff ngate net_subltap > 20

How can I solve the problem anyone have the idea and I will appreciate.
 

You need "tap" contacts closer to the transistor active region.
DRC should highlight the device in question. You may have
used an unreasonable geometry device (for noise / matching
reasons) which makes <20um gate*active - tap impossible,
this might make you change fingering etc. For analog where
possible I prefer guardrings to lonely "tap" contacts, "taps"
that pass latchup do not suffice to corral substrate noise
/ diffusing carriers from elsewhere.

Now, I would expect that your PDK documentation has a
decent discussion (with cartoons) of the tap / latchup
rules, which you could read.
 

Thank you for reply

I try to change the finger of the gate to get the suitable geometry but I have still got the same warning. and I add the tap closer to the transistor and the same warning. any other idea
 

Maybe "closer" is not "close enough". You have to measure
from the active-area edge of the "tap" to the most distant
active-area edge of the flagged device, and it has to be
less than 20um. There is no other idea than the plain
meaning of the error.

Does not the DRC display, show an outline flag on the
area of the device that is in violation?
 

I have two transistors (N-tape) they are the same dimensions and same connection and same finger of the gate but one of them has (ERC Warning: Latchup rule LAT3 distance s/d diff ngate net_subltap > 20) for one finger.

the first transistor (3 finger) just add tap and the problem the second transistor have 3 finger, only one finger has ((ERC Warning: Latchup rule LAT3 distance s/d diff ngate net_subltap > 20))
 

Turn off everything but active, N+ and P+, and measure
from the closest-in edge / corner of the ptap to the
furthest-out edge / corner of the nactive. Save and
post a screen shot with the ruler in place.
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top