Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Verilog code to find pulsewidth

Status
Not open for further replies.
D

DeepikaUpendra

Newbie level 1
Joined
Apr 10, 2017
Messages
1
Helped
0
Reputation
0
Reaction score
0
Trophy points
1
Activity points
9
Could anyone help me to write a code to find pulse width of a digital on time signal using verilog
 

The idea is simple like:

initial begin // or using always
@ posedge signal_A
rise_time = $time
@ negedge signal_A
fall_time = $time
end

You can find the correct syntax and functions for your purpose.
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top