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[SOLVED] [moved] synthesis error RTL schematic

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ecasha

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Hey guys,I am trying to view RTL schematic but its showing unexpected error. No errors are there in the code & 6 warnings HDLCompiler:1127:Assignment to c5 ignored, since the identifier is never used.
Whenever I try to view RTL schematic its showing the error and it terminates.What are the reasons for it?How to solve this problem?
error.JPG
 

Re: synthesis error RTL schematic

Unfortunately we have very little info to say for sure what might have gone wrong.

In order to view Xilinx RTL schematic, not only your code needs to be syntax error free but also compilation error free. So please re-check!
 

Re: synthesis error RTL schematic

No compilation errors.It gives the simulation results.
 

Re: synthesis error RTL schematic

Then as your screenshot says it is a Xilinx Application error, so there might be a Vivado bug. I think the people in the Xilinx forum will be able to guide you better.
 

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