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Design multiplexer in cmos ?

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Nhan95

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mux2_1_1.png5.5.png

Hi, I am design logic library in cadence, for multiplexer Y = S*D0 + (S')*D1, there are 2 structures to implement in the picture, which one should I choose ? Does it affect to signal strength when we use pass gate or tranmission gate to design logic circuit ?
 

Usually a library should have both. The transmission gate is faster than the pass gate, but loads the source and has higher output impedance.
 

The higher output impedance is in series with whatever
drives the input making timing even more fanout / wireload
dependent. Depending on minimum cell pitch you might
elect to buffer inputs and outputs with an inverter stage
(costing no-load delay, but greatly improving loaded delay
and edge-rate).

By the time you get to that level of complexity a 2-TINV,
2 INV implementation doesn't look so bad...
 

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