oAwad
Full Member level 2
Hello all,
I used HSIM to simulate a layout design with extracted parasitics operating with 200Mhz clk, the output of the simulation shows crosstalk between the clock signal and v(out[2]) as follows:
So are there certain procedures to take care of when designing layouts at high frequency ("Design compiler > SoC Encounter" flow)?
I used HSIM to simulate a layout design with extracted parasitics operating with 200Mhz clk, the output of the simulation shows crosstalk between the clock signal and v(out[2]) as follows:
So are there certain procedures to take care of when designing layouts at high frequency ("Design compiler > SoC Encounter" flow)?