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Schematics for Digital PDK library

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Nhan95

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I'm design a digital PDK library using cadence. For basic gate such as not, nand, nor,... I draw schematic in transistor level using nmos and pmos. But for bigger IC like full-adder, DFF,... Can I draw it using basics gate that I drew above or draw completely in transistor level.
 

If you have already drawn basic cells, you can also draw more complex devices using those existing basic cells as subcircuits,You don't have to re-draw all as transistor based.
 

If you have already drawn basic cells, you can also draw more complex devices using those existing basic cells as subcircuits,You don't have to re-draw all as transistor based.

But when I implement layout step and LVS, is it possible ?
 

But when I implement layout step and LVS, is it possible ?
Of course possible.LVS tool checks the layout as flatten and it does not know what is what, it just scan the layout, finds the semiconductor layouts an interpret these layout layers and other metallic connections and decide what type elements are their and compare with schematic.
 

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