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Literature review for post layout verification

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tarjina

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Hello everyone,
I am doing my thesis work on developing a design methodology which reduces the post layout simulation time for large analog designs.
I cannot find a proper literature that already talks about it. Whenever I search I get articles, books on Analog verification, mixed-signal verification, algorithms for verification but no-one speaks about the reducing run-time. If anyone can direct me to a one single literature regarding this, I would be really happy.
I am on a clock and kind of stuck!
Thanks in advance!!
 

I think this is heavily trodden ground, everybody wants
a simulator that can grind large netlists faster. And that
is the only difference between schematic and post-layout
simulation - netlist node- and element-bloat.

Now depending on the PDK's extract implementation
there can be things you do to the netlist that result in
a much better runtime (and lack of crashing). In particular
if your setup extracts each MOSFET finger as a separate
device, that's heinous. At one place I worked we tasked
one of the sysadmins to write a (PERL, I think) script
that scanned netlists for MOSFETs that had identical
D, G, S, B connectivity, counted them, and replaced
them all with one m=N device statement (commenting
the rest for traceability). Huge improvement, due to
de-bloating. I'm sure the same could apply to other
elements but MOSFETs are most commonly multi-
fingered and lazily extracted.

You're unlikely to find a paper to review, it was just
a bit of useful work done by someone who got no
glory.

But maybe this is the germ of an idea that will get
you past your academic gauntlet.
 

There is no glory in publishing a breakthrough in post-layout simulation time improvement - there is no much science to it (there may be a lot of insight and understanding and smart algorithms to it).
If someone comes up with something like that - it will be delivered to the world as a new software tool or a new functionality in existing tool, rather than a publication or a book.

This thing is very practical and very important, but not something that granting agencies would be happy to support, or journals would be eager to publish.

There are many things in life like that, glory and publications and grants go to "sexy" areas (graphene, carbon nanotubes, artificial intelligence), yet the real progress is driven by practical, un-sexy things (like silicon MOSFET, or copper instead of aluminum for interconnects).

In advanced nodes (16nm and below), shorting multi-finger devices will deteriorate accuracy to an unacceptable level - there are reasons why each instance is treated as a separate thing.
 

Am I supposed to make some turns in my life by reading your reply!!!!??!! when you say there is no much science to it.. you must have considered skipping all the journals and transaction papers. The thing is most of them are related to pure digital domain whereas I need something to quote from some real publications!
why wouldn't there be a series of publications regarding CAD/ design methodology! Have fun designing a device in 7nm with a poorly evaluated tool and wrapping up the business after 2 months..when the device fails in real life.
peace!!!
 

This seems to be a good overview of fast-SPICE technologies:

**broken link removed**
 

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