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Verilog Simple Spi Code

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Mucit23

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Hi Friends

I am trying to make a simple spi module with verilog. After I get the
Enable signal, I want to send the 8 bit data in series.
I've never worked with a verilog before.
I wrote a simple code but I do not know how to generate the clock
signal.

this is my Code;
Code Verilog - [expand]
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`include "cypress.v"
//`#end` -- edit above this line, do not edit this line
// Generated on 03/31/2017 at 15:12
// Component: ParalelToSerial
module ParalelToSerial (
  output  Busy,
  output  Clkout,
  output  Dout,
  input   Clkin,
  input  [7:0] Data,
  input   En
);
 
//`#start body` -- edit after this line, do not edit this line
    reg busy;
    reg dout;
    reg clkout;
    reg [3:0]cnt_spi;
    reg clk_count;
 
    assign Busy = busy;
    assign Dout = dout;
    assign Clkout = clkout;
 
    always @ (negedge Clkin)
    begin
       if(En == 1'b1 && busy == 1'b0)
       begin
         clkout=1'b0;
         dout=Data[cnt_spi];
         cnt_spi = cnt_spi + 1;
       end
 
       if(cnt_spi == 8)
         busy=1'b0;
       begin
 
       end
    end
 
//`#end` -- edit above this line, do not edit this line
endmodule


I will be glad if you help me. I'm just looking for a very simple
example of spi.
 

I've never worked with a verilog before.
I wrote a simple code but I do not know how to generate the clock signal.
Click to expand...

I would advise you to 1st write a 3 bit counter code in Verilog and then simulate it using a counter-testbench. It is not more than 1 days work, it will give you more confidence.

Then go for SPI. You have also not mentioned whether you want to design a SPI master or slave device.
Read this- https://www.edaboard.com/threads/182756/
There are also many codes available freely.
 

Hi friends
I've been doing research for a week. I have reviewed many codes on the internet, but they are very complicated.

Before starting this application, I did flashing LED and a few simple applications.

I'm testing it in real hardware. it works :)
Code: 
    always @ (posedge Clkin)  //1Khz Clock İnput
    begin
      if(counter== 500)
      begin
        counter=0;
        clkout = ~clkout;
      end
    end

my Verilog knowledge is at beginner level.

Now, I'm working on the PSoC devices. PSoCs have microcontroller and
PGA. PGA is programmed with verilog like fpga. I don't need SS in my
application because, I'm driving P10 LED panel, This panels only have
DATAIN and CLOCKIN inputs.

PSoCs are being designed with blocks. (my design in the attachment)
Now I need to write the contents of the Parallel_to_Serial module with
verilog.

I've sent a bit of bits to send
dout=Data[cnt_spi];
I just need to generate the SCLK signal.And a little control. (Busy
signal vs)
 

Mucit23 said:
Now I need to write the contents of the Parallel_to_Serial module with
verilog.

I've sent a bit of bits to send
dout=Data[cnt_spi];
Click to expand...

That is not a shift register, the dout line above describes a multiplexer. Don't use a multiplexer to shift data, that is what is done when someone doesn't understand that Verilog describes hardware it's not a software program.

Instead you should use the counter, cnt_spi, to decide if you shift Data or you load Data.

e.g.
Code Verilog - [expand]
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if (cnt_spi < 7) begin
  Data <= {Data[6:0], 1'b0};
else if (cnt_spi == 7) begin
  Data <= new_data;
end if;
assgin dout = Data[7];
 

    V

    Points: 2
    Helpful Answer Positive Rating
ads-ee said:
That is not a shift register, the dout line above describes a multiplexer. Don't use a multiplexer to shift data, that is what is done when someone doesn't understand that Verilog describes hardware it's not a software program.

Instead you should use the counter, cnt_spi, to decide if you shift Data or you load Data.
Click to expand...

@ads-ee

thank you for the replying

I'm reviewing the code you wrote. I did not understand how the code works.
Data <= {Data[6:0], 1'b0}; I did not understand what you were doing on this line.
How do you shift out the data?

The code failed at first. After some editing, it was compiled with noerrors.

Code: 
`include "cypress.v"

module ParalelToSerial (
	output  Busy,
	output  Clkout,
	output  Dout,
	input   Clkin,
	input [7:0] Din,
	input   En
);

    reg busy;
    reg dout;
    reg clkout;   
    reg [3:0]cnt_spi;
  
    always @ (posedge Clkin)
    begin
       if(En == 1'b1 && busy == 1'b0)
       begin       
            clkout<=0; //should be checked
            busy<=0;
            
            if (cnt_spi < 7) 
            begin
              Data <= {Data[6:0], 1'b0};
            end
            else if (cnt_spi == 7) 
            begin
              Data <= Din;
            end
            cnt_spi = cnt_spi + 1; 
       end
       
       if(cnt_spi==8)
       begin
         busy<=1'b1;
       end
    end

    assign Busy = busy;
    assign Dout = Data[7];
    assign Clkout = clkout;
    
    
//`#end` -- edit above this line, do not edit this line
endmodule

Now I don't know how to generate the clock signal. Could you help in this?
Thank you
 

{} is the concatenation operation, so it drops the MSB of Data and appends a 0 to the end of the 7-bits to produce a new shifted 8-bit value which is assigned to the 8-bit Data.

You need to have another counter that enables the shift operations between clkout output changes. SPI uses opposite edge clocking to transfer data so you would shift when the clock is either high or low (depending on the mode) and then have a Clkin cycle where the clkout changes.

Do a search on the SPI waveforms.

BTW the above code does have an error you never declared Data so it would be a 1-bit wire, which should cause an error. Also reg dout; isn't used anywhere. You have another signal named Dout. This is a bad practice having multiple signal names with the only difference being case. Verilog respects case unlike VHDL. If you want signals with random case to all be the same signal use VHDL. I also dislike the camel case names, makes you have to hit the shift key every time (sometimes multiple times in a single signal name) and that causes carpal tunnel if done too much. Just talk to older software types that love camel case most of them have wrist problems.
 

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