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Problems writing Verilog testbench for 4:1 mux

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pakha

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Hi,

I am trying to write verilog code for 4:1 mux using rtl but I am finding difficulty in the test bench code. please correct me

The code goes as follows

Code Verilog - [expand]
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module multiplexer(a,b,c,d,s,out);
      input a,b,c,d;
      input[1:0]s;
      output y;
      reg y;
      always@(a or b or c or d or s)
      begin 
      if(s==2'b00)
      y=a;
      elseif(s==2'b01)
      y=b;
      elseif(sel==2'b10)
      y=c;
      else
      y=d;
      end
      endmodule
 
      Test bench
   
      module tmux; 
      wire y;
      reg a,b,c,d;
      reg s0,s1;
      mux4 mux(.y(y),.a(a),.b(b),.c(c),.d(d),.s0(s0),.s1(s1));
      initial
      begin
      s=0, a=0,b=0,c=0,d=0;
      #10a=2'b11;
      #10b=2'b11;
      #10c=2'b11;
      #10d=2'b11;
      #10sel=2'b11;
      end
      endmodule;
 
Last edited by a moderator:

Re: Verilog Hardware description language

lines 1-4: sucky antiquated usage of pre-Verilog 2001 module port declaration syntax....Use Verilog 2001 syntax it's much cleaner and requires no repeating of the post names in two places.
lines 10, 12: elseif is not a proper verilog keyword it is: else if
line 12: sel is not declared and is probably supposed to be s
line 25: s0 and s1 are NOT the way you define the ports for a bus .s is the bus name and using your silly names s0 and s1 in the testbench the connection should be .s({s1,s0}).
lines 29-33: #10a, etc might not even compile correctly as there is no white space separating the number from the signal name. Use whitespace in your code from now on it's free (or nearly so) and it makes code much easier to read, instead of a packed messes of characters you have to really look at to determine if something starts or ends. Also learn to indent code, haven't you ever written C and been told to indent stuff?
line 33: what is sel it's not defined in your tmux module.

maybe you should learn Verilog syntax before writing code. You should also learn to proof read you code before posting these are ALL easy to spot mistakes.

- - - Updated - - -

BTW, you should use an editor that has syntax highlighting, then you wouldn't have the problems with incorrect keywords like the elseif. You're probably using some crappy "editor" like windows notepad (sucks) or wordpad (sucks even more).
 

Need Verilog 4:1 mux testbench

Hi guys,

Can anyone provide me the test bench for 4:1 mux using structural or gate level modelling in verilog?
 
Last edited by a moderator:

Re: Need Verilog 4:1 mux testbench

pakha said:
Hi guys,

Can anyone provide me the test bench for 4:1 mux using structural or gate level modelling in verilog?
Click to expand...

No, I'm not writing one for you. Don't be lazy. Try writing one first, if you don't know how there are many, many resources on the internet for you to look at. Try using google and the search term: "verilog testbench", or perhaps you want someone to do that for you too...:thumbsdown:

If you already wrote one and it doesn't work, then instead of asking someone to write one for you, how about posting it so we can help you fix it. You will learn more by fixing your mistakes than someone giving you a working testbench...

- - - Updated - - -

Just realized you already had a thread on this very subject. I guess I issue another infraction and merge this thread with you other thread.

- - - Updated - - -

You need to learn Verilog before you start trying to code anything. You currently have so many typos and just bad syntax that the testbench won't even compile.
 

Re: Need Verilog 4:1 mux testbench

Hi,

I am trying to design 2 stage 16 bit pipelined adder using 8 bit adder and i have worked very very hard on this and I sat down and finally wrote the code.
-----------------------------------------------

Code Verilog - [expand]
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module pipelineadder(input[15:0]a,b,
                      input stage1,stage2,p,q,
                      input clk,cin,rst,
                      output [16:0]sum,
                      output cout);
 
    
    always@(negedge clk);
    begin
    add(.a(a[7:0]),.b(b[7:0]),.cin(cin),.p(p));
    stage1 <= p;
    add(.stage1(stage1),.a(a[15:8]),.b(b[15:8]),.q(q));
    stage2 <= q;
    end
    assign cout<=stage2;
    task automatic add(input p, input q, output cout);
    begin
    cout=p+q;
    end task
    end
    endmodule


and Test Bench

Code Verilog - [expand]
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module tpipelineadder;
reg [15:0]a,b;
wire [16:0]sum;
wire p,q,stage1,stage2;
reg cin;
wire cout;
 
pipelineadder myadd(.cout(cout),.a(a[15:0]),.b(b[15:0]),.sum(sum[16:0]),.cin(.cin),.p(p),.q(q),.stage1(stage1),.stage2(stage2));
initial
begin
 
#10 a=15'b0101010010101001;
#10 b=15'b1010010101010101;
#10 $stop;
end 
endmodule


kindly help :)
 
Last edited by a moderator:

It will not be a good idea to ignore #4 and jump on a new task (pipelined adder).
 

dpaul said:
It will not be a good idea to ignore #4 and jump on a new task (pipelined adder).
Click to expand...

Worse yet they already have a pipelined adder thread, and I'm too tired of this time wasting user to give them an infraction for hijacking their own thread with an off topic post.....

pakha said:
module pipelineadder(input[15:0]a,b,
input stage1,stage2,p,q,
input clk,cin,rst,
output [16:0]sum,
output cout);


always@(negedge clk);
begin
add(.a(a[7:0]),.b(b[7:0]),.cin(cin),.p(p));
stage1 <= p;
add(.stage1(stage1),.a(a[15:8]),.b(b[15:8]),.q(q));
stage2 <= q;
end
assign cout<=stage2;
task automatic add(input p, input q, output cout);
begin
cout=p+q;
end task
end
endmodule
Click to expand...
Only one person on edaboard would agree with the use of a task in synthesizable code (I don't agree and think it is never appropriate).

If you are a student in school then you are definitely not being taught anything useful for real world designs.

I noticed your add task is missing an input you have in the locations where it is used, namely cin is not on the task definition. Do you ever look at your code or are we supposed to be your proof readers?

You write Verilog like you want it to be Python, C, C++ or some other software programming language. Draw a schematic of SSI and MSI components first, 7400 series parts before writing any code. You will design better hardware if you understand you are not writing programs but are writing something that is more akin to ICs on a board. Instances in your code are the ICs. The top level file is your PCB.

- - - Updated - - -

Do you even know the difference between an input port and an output port on a module declaration and how it is used? You have signals like stage1, stage2, p, and g as input ports of the module but are generating them inside the module for use only inside the module. That is a compilation error and shows you haven't even read a Verilog book. At the very least try to compile your code in a simulator BEFORE posting it. When you have NO syntax mistakes and blatant errors in your code, then you can post the code, otherwise I won't even consider looking at or helping you with your next post.
 

Another obvious mistake is the use of a .port_name that doesn't even match the definition of the inputs and outputs of the add task.

What crappy website are you using to learn Verilog? It's obviously not from a book. As you seem to have a very poor understanding of what goes in the .port_name and what goes in the (inter_connect_name_ie_wires_hooking_up_ics)
 

In this case, the task doesn't serve any purpose -- "y <= a + b + c" is more clear.

The design also is mispipelined.
 

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