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msdarvishi

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Dear all,

I am coming back to this issue to say the great part of problem issued in the post here got solve but, a new restriction exists that I do not know is it a restriction in Tcl scripting or it can be solved.

If you look at my attached snapshot, there are 2 PIPs highlighted with red circles that the first in bottom is an input PIP and the one at top is an output PIP. Using Tcl scripting, fortunately I could connect other parasitic wires to the input PIP at bottom as shown with white wires in the picture. You see, all the wires connected to this PIP are exiting this PIP.

The problem is when I am trying to connect a parasitic wire to the PIP at top (please see the second attached snapshot) where the parasitic wires are entering that PIP since the PIP is an output. When I try to connect any of them to that PIP at top, I receive the following error which means the resource of that wires is unknown and it is correct since it does not recognize where that wire comes from !!


Code:
set_property route { { CLBLL_LL_AMUX  CLBLL_LOGIC_OUTS_L2  IMUX-L4 SE2END2  } } [get_nets  {Inst_StartPoint_DFF/Qs}]
Code:
[COLOR="#FF0000"]ERROR: [Designutils 20-941] Did not find node resource, CLBLL_LOGIC_OUTS_L2, downhill from node, CLBLL_L_X2Y51/CLBLL_LL_AMUX.
Downhill node choices include:  CLBLL_L_X2Y51/CLBLL_LOGIC_OUTS20 [/COLOR]
.
Can anyone help me how to solve this problem ?


Thanks and Regards,
 

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Without the design database it will be very hard to figure out what is wrong. None of those white connections seems to be showing in the second picture, so is that input PIP even connectable to the Output PIP you show in the second picture?

My guess would be that the set_property_route command may have something wrong with the list of nodes. Possibly using the output PIP is not what you want to do, but I can't check this as I don't have an equivalent design.
 

Without the design database it will be very hard to figure out what is wrong. None of those white connections seems to be showing in the second picture, so is that input PIP even connectable to the Output PIP you show in the second picture?

My guess would be that the set_property_route command may have something wrong with the list of nodes. Possibly using the output PIP is not what you want to do, but I can't check this as I don't have an equivalent design.


Dear @ads-ee,

Thanks for your reply. Infact, concerning your question, the input PIP is connectable to the output PIP in order to configure the routing path. Meanwhile, I am trying to connect some parasitic wires to the input and output PIPs as well.

Also, concerning your point that you've said : "None of those white connections seems to be showing in the second picture", YES it is correct and normal because in the second picture I did click on the output PIP and so only its corresponding wires with input direction are shown while in the first figure, I did click on the input PIP and all the while wires correspond to the input PIP with the exit drection.

The problem that is stated here is that the script using the set_property route command does not accept any wire to be connected to the output PIP and returns the error mentioned in my initial post ! It is quite weird !
 

The problem that is stated here is that the script using the set_property route command does not accept any wire to be connected to the output PIP and returns the error mentioned in my initial post ! It is quite weird !

I don't believe you can specify output nodes you can only specify destination input nodes (loads). Try using the destination of that output PIP.

I might be wrong, but I think the command also has a route through option of some sort that perhaps the output PIP could be included in...along with the destination node.
 

I don't believe you can specify output nodes you can only specify destination input nodes (loads). Try using the destination of that output PIP.

I might be wrong, but I think the command also has a route through option of some sort that perhaps the output PIP could be included in...along with the destination node.

Dear @ads-ee,

I completely agree with you ! Lots of trials we me were failed and I think no more trial is required since it has a logic reason : A destination output cannot be specified with an unknown source wire !!

Meanwhile, I will keep this post open and I will try to find a reasonable solution or another path for my trials and I will get back to come up with the new findings.

Sincerely,
 

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