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Standard interface for DAQ IP

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viyaaloth

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Dear All,

I am developing a DAQ IP Core which include a generic DAQ IP and ADC specific module IP. I need a standard Interface between these two module for data transfer. Which one I have to choose. Please help with your valuable suggestions. Which one is good among UART, SPI, ethernet.

Regards,
viyaaloth
 

It depends on a lot of things that you haven't mentioned, most specifically speed. And data width. And cost. And distance. And everything else.

UART is good
SPI is good
ethernet is good
I2C is good
....
 

Or to put it another way expect useful data transfers over the different interfaces as approximately:

I2C - low Kbps range
UART - up to 100 Kbps range
SPI - 10's of Mbps range
Ethernet - high 100's of Mbps range, using UDP you can easily achieve 800+Mbps throughput.

So whatever your data rate requirements will determine the interface you'll need.
 
Inter IP communication in FPGA

Hi all,

I would like to know about inter IP communication in FPGA. I am developing a design in FPGA which includes two IPs. One is capturing data from ADC IC module. Its sole function is to forward data to the second IP(Data acquisition IP). So I need a communication between these two IPs. Since FPGA will support parallel connections I am looking for a parallel interface. Is it possible to use any parallel interface, hence suggest me some interfaces. If it is not available, what will be the solution for inter IP communication in FPGA.


Reagrds,
Viyaaloth
 

Hi,

it depends on your needs.

Maybe a straight parallel interface with just one "clock" signal is sufficient.
Maybe you want some FIFO, this is good for crossing clock domains
Or maybe use dual port RAM. This could be a benefit if you want to block process data with FFT.

It depends on ADC speed, system clock(s) and maybe channel count, processing type and processing time, limitations in latence timing....

Klaus
 

Hi Klaus,

Thanks for your reply. What do you think about axi stream or avlon mm if.. Is it possible to use any of them. or any other interface availabe for inter IP communictaion with in FPGA..?
 

I would like to know about inter IP communication in FPGA. I am developing a design in FPGA which includes two IPs. One is capturing data from ADC IC module. Its sole function is to forward data to the second IP(Data acquisition IP). So I need a communication between these two IPs.

By the above description, it is not too clear if this communication will be in master-slave mode, if it could be half-duplex, etc. There are factors that will determine/restrict your choice, and you should take them into account.
 

Using a standard streaming interface would be my suggestion at least for high data rates. If the data rate is only a small fraction of the design clock rate, you can probably use simpler handshaking methods, but there may be reasons to use the streaming interface though.
 

Hi Andre_teprom,

Yes. It is using master-slave communication and half-duplex. How it is possible for inter-IP communication. Avalon interface from Altera will be a solution.? whether I can use AXI Stream interface.?

- - - Updated - - -

Hi FvM,

Could you please suggest me some standard streaming interfaces that I can be used in my design.
 

You seem to be avoiding giving us enough information to make intelligent responses.

WHAT IS YOUR DATA RATE?

As previously suggested, in might just be simplest to use a parallel interface. Maybe you need to double-buffer it. But there is nothing you've said that would indicate you need anything fancier than that.
 

Generic interface for DAQ IP

Dear All,

I am developing a design which includes two IPs. One is ADC specific IP which will acquire a single sample and returns to the second IP that is DAQ IP. So I need a generic interface between these two IPs for inter IP communication within FPGA. I am concentrating a generic standard interface, so that it could be compliant for all type of ADC( for example 16-bit ADC, 24-bit ADC). currently I am using 8-bit ADC. My DAQ IP will support 100 MSPS.

Regards,
Viya
 

Re: Generic interface for DAQ IP

So I need a generic interface between these two IPs for inter IP communication within FPGA.

Show us the top-level ports for both IPs (consider the 24-bit ADC). That will enable us to better answer the question.
 

Re: Generic interface for DAQ IP

still it is in initial stage. Any of the IP's architecture is not yet conformed. I am doing a research on that. what is the suggestion on AXI streaming interface ??.. or Can you suggest any simple parallel interface in which data width can be parameterized. So that I can use any of the ADC with different data width..

- - - Updated - - -

DAQ IP is not supporting any high data rate . Maximum is 100 MSPS. Could you please suggest any simple parallel interface?. If it is possible to parameterized the interface for data width, I can use it for 4-bit ADC, 12-bit ADC etc...
 

Synchronization logic for DAQ

Dear All,

Can anyone tell me what is the role of synchronization in data acquisition IP in terms of hardware design. Whether synchronization is a mandatory for DAQ IP?


Regards,
Viyaaloth
 
Last edited by a moderator:

AXI-S is good. Its simple yet powerful.
If master and slave have different data widths, then a AXI-S upsizer/downsizer IP can be used.
 

Okay. Let me ask you two more question.
Is it applicable to create my own parallel interface?. If it possible, then this interface needs to be compatible with any ADC IP that I will create(4-bit ADC, 12-bit ADC etc...). How can I ensure that it is compatible to all ADC IPs.?

If i could use AXI-S interface what is the advantage over a simple parallel interface?
 

first of all, I would not consider 100MSPS 'low data rate'. When you speak of 'ADC IP' what do you mean? Do you mean the interface to the actual ADC chip, or something else? If you mean the chip interface, there's no way to make it generic, they're all different.
 

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