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Stateless Module in HDL design

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viyaaloth

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Dear All,

I have to work on a ADC IP which should be ideally stateless. What is mean by a module "stateless". Please let me know the possible answers.


Regards,
Viyaaloth
 

I have no idea. Any design that has any ability to change a single bit from '0' to '1' has 2 states. So unless it means a design that just drives constants, it sounds like a strange concept.
 

In this context, it means you don't try to make a HW implementation of a smart ADC. You don't have any automatic gain controller. You don't have any automatic sample-rate conversion, PLL, resampler, etc... No adaptive/directed equalizers of any sort. any gain scheduling must be from another input and not based on previous inputs. All of these are examples of a system that has state -- previous inputs affect current inputs.


It means that each input sample is just reported and not used to modify how further inputs are sampled.

For implementation purposes, these can be be pipelined. There is still a distinction between cycle delay vs sample delay.
 
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