Need help in deciding the appropriate interface in Vivado HLS

Hi there,

I am developing a design in Vivado HLS which is compiling and giving the proper results.
Now i need to generate the interfaces so that i can program it on the FPGA board. I have assigned the following interfaces to the core function:

Function:
void accel_core (data_in sin_in,data_in cos_in,data_t imgons [MAT_IN_ROWS][MAT_IN_COLS],data_t out[MAT_SIZE][MAT_SIZE], int index_pass)
{
#pragma HLS INTERFACE s_axilite port=return bundle=cntl
#pragma HLS INTERFACE s_axilite port=index_pass

#pragma HLS INTERFACE s_axilite port=cos_in bundle=cntl
#pragma HLS INTERFACE s_axilite port=sin_in bundle=cntl

#pragma HLS INTERFACE axis port=out
#pragma HLS INTERFACE axis port=imgons
}

The matrix dimension is as follows:
#define MAT_IN_ROWS 128
#define MAT_IN_COLS 100
#define MAT_SIZE 64

sin_in, cos_in, and index_pass are just parameters.

Fixed point definition:
typedef ap_fixed<16,10> data_t;
typedef ap_fixed<12,2> data_in;


But when i do C-RTL cosimulation it fails giving the following message:

Can some one help me in generating appropriate synthesizable interface for the design?