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Signal deleted in questasim

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Binome

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Hi,
I'm simulating a vhdl design in questasim. One of the signals is deleted when optimization is used and I'd like to understand why.
This signal is directly connected to an output of the simulated component and I can see it changing when simulating with no optimization. Is there a detailed report explaining why it is deleted?
Thank you for any help.
 

No there is not (afaik). But you could always invoke vsim with -novopt, or if you want only specific entity level access, you can use -voptargs="+acc=<entity path>" (or just directly on vopt) to prevent optimisation on specific parts of the hierarchy, to allow faster sim speed by optimising non-visible parts.
 

Now it's OK. That was because no default value was specified for my output port. Questa removed it because of that !
 

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