MOd24
Newbie level 2
hello everyone,
I am trying to set up a VHDL testbench for my project in Vivado. I want to make a simulation from the top level perspective and not just simulating an IP core. Vivado already added the HDL wrapper for the simulation, but I'd rather use my own testbench instead of the wrapper.
I started creating a new file, copied and pasted instantiation of a module however, that module then appears with a question mark in the sources explorer indicating that the module is not recognized.
When I instantiate the block design wrapper the module is recognized.
In the simulation settings, the simulation set is the same, my testbench is in the same directory as the HDL wrapper and 'include all design sources for simulaiton' is checked.
so why is it not working???
I am trying to set up a VHDL testbench for my project in Vivado. I want to make a simulation from the top level perspective and not just simulating an IP core. Vivado already added the HDL wrapper for the simulation, but I'd rather use my own testbench instead of the wrapper.
I started creating a new file, copied and pasted instantiation of a module however, that module then appears with a question mark in the sources explorer indicating that the module is not recognized.
When I instantiate the block design wrapper the module is recognized.
In the simulation settings, the simulation set is the same, my testbench is in the same directory as the HDL wrapper and 'include all design sources for simulaiton' is checked.
so why is it not working???