Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Synthesizing with ISE

Status
Not open for further replies.
M

mahmood.n

Member level 5
Joined
Dec 2, 2011
Messages
85
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,286
Activity points
2,046
Synthesizing a very simple two-state FSM (Moore machine) with ISE results in the following schematic. Thing is that the 2-LUT has no control input. So, it is not clear for me, how that LUT work actually. Is there something messing?
 

Attachments

  • fsm.jpg
    fsm.jpg
    56 KB · Views: 65

Without supplying the code you synthesized nobody can say if the LUT is correct or not. Though based on your description it probably is correct.

There is one input to the FSM from an external pin and the output of the FSM is fed back to the LUT. So unless you are saying you have 2 or more inputs to the FSM and you only have one showing then there isn't anything wrong.

FYI, A 2-input LUT (look up table) can produce any function of those 2 inputs. Including the state transitions for a s0-s1 state FSM.
 

I have attached the code. My question is that a 2-LUT has three inputs (one is the control input) and an output

Code: 
             +-----+
             |     |
     a1----- |     |
             |     |-------- y
     a2----- |     |
             |     |
             +-----+
                 |
         c-------+

that means y=c'.a1 + c.a2
However, the LUT shown in the ISE has two inputs only.

Code VHDL - [expand]
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41

library ieee;
use ieee.std_logic_1164.all;
 
entity fsm is
    port( x, clk, rst: in std_logic;
          y: out std_logic);
end;
 
architecture x of fsm is
    type state is (SA, SB);
    signal cu_state, nx_state: state;
begin
    process(clk, rst)
    begin
        if rst = '1' then
            cu_state <= SA;
        elsif (clk'event and clk = '1') then
            cu_state <= nx_state;
        end if;
    end process;
    
    process(x, cu_state)
    begin
        case cu_state is
            when SA =>
                    y <= '0';
                    if x = '0' then
                        nx_state <= SA;
                    else
                        nx_state <= SB;
                    end if;
            when SB => 
                    y <= '1';
                    if x = '1' then
                        nx_state <= SA;
                    else
                        nx_state <= SB;
                    end if;
        end case;
    end process;
end;
 

Your design does only need 2 inputs: X and current state. the state will be encoded as a single bit as it only has 2 states. So the RTL diagram in your first post is exactly as I would expect.
 

I know it is correct, but I don't know why the LUT in the diagram has two inputs. As I said and based on what we have learned, a 2-LUT has 3 inputs as I show in my previous post. If you insist that the diagram is OK, then please write the boolean equation of the D (input flip flop)
 

TrickyDicky, that is not an AND gate. It is an XOR gate. To be sure, I synthesized the same code with Quartus and gave me better understanding. Please see the picture.

If one wants to put a 2-LUT instead of an XOR gate, he has to do like this

Code: 
             +-----+
             |     |
     X ----- |     |
             |     |--------D
     X'----- |     |       
             |     |         
             +-----+       
                 |         
                 +------ Y

But I dont' see such thing in the ISE's output. The ISE feeds X (input only) and Y without any control input. Still I think the ISE's output is vague
 

Attachments

  • qu.jpg
    qu.jpg
    23 KB · Views: 50

I really dont understand what you're getting at? ISE and Quartus have produced the same circuit. IE. Y' is dependent on Y and X only ie. 2 inputs.
I dont understand by what you want with some imaginary C input? using X, X' and Y would give you a 3 input LUT.
 

mahmood.n said:
As I said and based on what we have learned, a 2-LUT has 3 inputs as I show in my previous post.
Click to expand...

Your instructor is misleading you if this is what you were told...

A two input LUT does this:

Code: 
 a b | c
-----+-------
 0 0 | f(0,0)
 0 1 | f(0,1)
 1 0 | f(1,0)
 1 1 | f(1,1)
There is no control signal there are two inputs and one output...a two input look up table (looking up a value for c).
 

CataM said:
He is confusing LUT with MUX. Look in post #1 what is the name of the LUT: Mmux
Click to expand...

Ah, that makes sense...the two input LUT contains a mux to select the FSM branch taken and the resulting next state.

Though the OP doesn't seem to understand that the two bits being muxed are both state bits with the X input selecting between SA or SB states, which just so happens to be cu_state or NOT cu_state.
 
Yes I was thinking about MUX. Thanks for the explanations.
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top