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    Critical path of combinational circuit

    I have synthesized a combinational circuit with Quartus and I am able to see the mapped logic elements in the chip planner. My question is, how can I get the critical path delay since the logic elements are placed far away?!! I think four logic blocks should be placed close together.

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    Re: Critical path of combinational circuit

    If is a synchronous circuit, then as long as it meets timing between the registers then there is no problem..



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    Re: Critical path of combinational circuit

    But I want to see a report with some values.



    •   Alt30th March 2017, 14:04

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    Re: Critical path of combinational circuit

    Use time quest. If you report the clocks you can view all paths in that clock domain. They can be sorted by slack. It will show the timing per path.



    •   Alt30th March 2017, 14:54

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    Re: Critical path of combinational circuit

    I opened Time Quest and clicked on "Report Path". What should I enter in the window? I searched for some tutorials about that but didn't find a straight forward tutorial for beginners.



    •   Alt30th March 2017, 17:24

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    Re: Critical path of combinational circuit

    The ... to the right of the from text box should open a list of the items you can select (if I recall correctly, it's been nearly a decade since I used Quartus).

    You never did say if your design has clocks or not...

    If it's all combinational like you implied with your first post then you should just put input pins in the from box and output pins in the to box.

    Also if you didn't supply any constraints for the input/output delays (based on the info in the picture) then you shouldn't expect the cells in the design to be placed near each other as you supplied no information on the timing requirements. If you want to have a timing objective then you'll need a virtual clock for the input/output delay constraints and appropriate set_input_delay and set_output_delay constraints to give you the require Tpd of the combinational path.



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    Re: Critical path of combinational circuit

    The circuit is a 32 bit adder which uses 4-bit carry look ahead blocks. So there is no clock there. In that dialog box, I entered "ci" as "From Node" and "co" as "To Node" (carry to carry path).
    The output of the report is

    Code:
    From Node          ci
    To Node          co
    Delay          30.618
    What is the time unit?



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    Re: Critical path of combinational circuit

    I'd say it is in ns, hard to imaging an FPGA that can manage a 30GHz add (30.6 ps).


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    Re: Critical path of combinational circuit

    Remember, that any timing information you get will be using the timing model selected as default, which I think is th 85C model. This means that the timing in the real circuit is likely to be better than reported, and will vary with process (ie from chip to chip), voltage and temperature. You should not rely on any timing information if you're trying to balance the delay between parallel paths.

    The only way to guarantee timing (and the way FPGAs are built) is to use a clock for your design.


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    Re: Critical path of combinational circuit

    Hello there,

    How can we find the critical path? Like, in the image below, the yellow line shows the critical path. My question is how can we identify that the path of input B is the critical path and not that of A or C or D.

    Click image for larger version. 

Name:	Untitled.png 
Views:	4 
Size:	22.0 KB 
ID:	138552

    Thanks in advance :)
    Last edited by dzafar; 6th May 2017 at 02:21.



    •   Alt6th May 2017, 01:51

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    Re: Critical path of combinational circuit

    Using timequest you can setup a report to cover an entire set of registers on a single clock, or the timing between two nets. Either way, it will always list the results with the slowest (longest) path first.



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    Re: Critical path of combinational circuit

    @TrickyDicky,

    In the image I attached last time, the path delay is 5ns (say each gate has a delay of 1 ns and and all inputs are sent at time 0). What I am confused about is that the 5ns delay can very well have a path

    C -> AND -> INV -> OR -> AND

    Also, the path below gives the same delay of 5 ns
    D -> AND -> OR -> AND.

    I am confused about what made us choose the path to start at B? Is it max number of gates? If so, why not choose C instead?!

    Thanks in advance :)



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    Re: Critical path of combinational circuit

    If each gate had its own delay, then the party with most gates will have the highest latency. But in an FPGA there are no gates, just luts, and registers, and routing. So is this a real life question, or just an academic question (that is a very simplified version of reality).



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