Sumathigokul
Member level 1
Hi All,
I want to generate a true random number in Actel ProAsic3 FPGA development board which operates at 48 MHz. I tried to implement it using ring oscillators (RO) and used the system clock i.e. 48 MHz as sampling frequency. As the sampling period is around 48 MHz => 21 ns, the RO period should at least be double the sampling frequency, i.e. 42 ns, means that my RO has approximately 41-45 inverter (NOT gates). Hence, the resource utilization of my target design will be increased by 45 additional core cells (approximately for RO + D flipflop), but i may only have hardly 10-15 additional core cells left unused in the device.
I need any suggestion to implement the optimized version of true random number generator as per my system clock frequency i.e. 48 MHz.
Thank you in advance.
I want to generate a true random number in Actel ProAsic3 FPGA development board which operates at 48 MHz. I tried to implement it using ring oscillators (RO) and used the system clock i.e. 48 MHz as sampling frequency. As the sampling period is around 48 MHz => 21 ns, the RO period should at least be double the sampling frequency, i.e. 42 ns, means that my RO has approximately 41-45 inverter (NOT gates). Hence, the resource utilization of my target design will be increased by 45 additional core cells (approximately for RO + D flipflop), but i may only have hardly 10-15 additional core cells left unused in the device.
I need any suggestion to implement the optimized version of true random number generator as per my system clock frequency i.e. 48 MHz.
Thank you in advance.