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6G/12G-SDI : Location of MGTREFCLK/ Range of QPLL

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Hi,
I am trying to run following reference design for 6G-SDI:
https://www.xilinx.com/support/docu...e-sdi-interfaces-7series-gtx-transceivers.pdf

As mentioned in its page 9, MGTREFCLK input is provided as follows:

Code Verilog - [expand]
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// MGTREFCLK input buffers
(* LOC = "IBUFDS_GTE2_X0Y6" *)
IBUFDS_GTE2 MGTCLKIN0 (
.I (FMC_HPC_GBTCLK0_M2C_C_P),
.IB (FMC_HPC_GBTCLK0_M2C_C_N),
.CEB (1'b0),
.O (mgtclk_148_5),
.ODIV2 ());
(* LOC = "IBUFDS_GTE2_X0Y7" *)
IBUFDS_GTE2 MGTCLKIN1 (
.I (FMC_HPC_GBTCLK1_M2C_C_P),
.IB (FMC_HPC_GBTCLK1_M2C_C_N),
.CEB (1'b0),
.O (mgtclk_148_35),
.ODIV2 (drpclk_in));

But I didn't understand the location index(X0Y6, X0Y7) after IBUFDS_GTE2_. How it is determined? if I am using another transceiver having different MGTREFCLK, does this index also change or always reamains same?

Furthermore, it is written that QPLL is operating in range 1. How and where to set range 1 (in case of 6G) and range 2(incase of 12G, see page 10/11) in the code?
Actually the refernce design is written for 12G in xc7k325t-3 and I am modifying it for xc7k325t-2 with the help of wrapper file given for 6G.
 
Last edited:


shaiko said:
The transceivers on the Xilinx's V7 have dedicated clock routes. So the index will have to be changed accordingly.
https://www.xilinx.com/support/documentation/user_guides/ug476_7Series_Transceivers.pdf
Look in the page 347 and beyond
Click to expand...

Hi,
what you are saying is for Transceiver Channel and common location(that I can see after opening synthesized/implemented design and switching to clock planning. see attachment) but I am asking about index for the location of Transceiver reference clock.

I am not sure but I guess:
Bank 115: X0Y0 and X0Y1
Bank 116: X0Y2 and X0Y3
Bank 117: X0Y4 and X0Y5
Bank 118: X0Y6 and X0Y7

Still looking for range 1 and range 2 setting for QPLL??
 

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