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Verilog-A convergence issues

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mr_mosfet

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Hi,

I'm new to Verilog-A I am having convergence issues with a device I modeled in Verilog-A. When I have the device simulated in parallel with a time varying voltage source then the simulation seems to work okay. The issues arise when I try to simulate transient behaviour of my device in series with an added resistor and the voltage source in parallel with both the series resistor and Verilog-A device (as seen in image if I added it correctly).

The code for the device is below.

Code:
`include "constants.vams"
`include "disciplines.vams"

module test_func(p,n);

	inout p,n;
	electrical p,n;

	//files for reading/writing
	integer mcd, fp;

	real data, v_present, v_step;

	real preisach_density[0:256];// all elements should add up to 1
	real domain_states[0:256];// all elements should be -1 or +1 (depending on polarity)
	real polarization;//polarization (between -Pr and +Pr)
	
	real polarization_prev, polarization_next;
	real time_prev, time_next;

	integer i, j, k;//used in loops

	integer rows, columns;//describes area scanned from applied voltage
	integer rows_total, columns_total;//gives number of rows and columns in the grid ("rows" and "columns" should not exceed these values)
	
	analog begin	

		@(initial_step) begin

			//read data from csv file and transfer it to verilog-A array variable
			//data stored in csv file should be preisach distribution
			//csv file should have the same number of elements as arrays "preisach_density" and "domain_states"
			mcd=$fopen("test6.csv","r");

			while (!$feof(mcd)) begin

				$fscanf(mcd,"%f", preisach_density[i]);
				domain_states[i] = 1;

				i = i+1;
      			end

		//****************** v_step should be changed, should equal resolition of grid spacing
		v_step = 0.1; //arbitrary

		rows_total = 1.6/v_step;//the maximum anticipated applied input voltage divided by the resolution of the grid cells
		columns_total = 1.6/v_step;//the minimum anticipated applied input voltage divided by the resolution of the grid cells

		polarization_prev = 0;

		time_prev = 0;
		time_next = 0;
		
		end

		if (V(p,n) < 0) begin

			rows = V(p,n)/(-v_step);

			for(j = 0; j < columns_total; j=j+1) begin

				for(k=0; k<rows; k=k+1) begin

					domain_states[k*columns_total + j] = -1;

				end
			end
		end

		if (V(p,n) > 0) begin

			columns = V(p,n)/(v_step);

			//value compared to j should equal number of columns in array
			for (j=0; j<columns * rows_total ; j=j+1) begin

				domain_states[j] = 1;

			end
		end

		polarization = 0;
		for (i=0; i<columns_total*rows_total; i = i+1) begin

			polarization = polarization + preisach_density[i]*domain_states[i];

		end

		
		polarization_prev = polarization_next;
		polarization_next = polarization;
		time_prev = time_next;
		time_next = $abstime;

		I(p,n) <+ (polarization_next - polarization_prev)/(time_next - time_prev);

	end

endmodule

The error I get is:

Error (SPECTRE-16080): No DC solution found

I also get "Array access out of bounds" errors when the device is simulated in the circuit shown but this does not occur when it's just the device in parallel with the voltage source with no resistor. Does anyone have suggestions for how I can solve these issues?
 

I would put a trivial series resistor between any veriloga
block pin, and the larger schematic. Any parallel "stuff"
should be attached to the outboard ends. In my experience
this forces the conversion of port I, V to be done in a way
that works for SPICE / Spectre. And it lets you probe a
well behaved, no-mystery primitive element which is hard
(or impossible, depending on code) to do on a bare veriloga
entity's ports.
 

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