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Srio ipcore. can't simulate when using 3.125g mode.

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bravoegg

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I'm trying to use Xilinx Srio Ipcore and could generate the example design( generated automatically by Vivado) which could be simulated properly. However it only simulates properly when I change nothing in the ipcore GUI.

The default transfer frequency is 5Gbaud. I will need to use 3.125Gbaud .
But after I set the transfer frequency to 3.125Gbaud and leave other items as it is, and again generate the example design. Later in the simulation the link_initialized and port_initialized signals are never valid.

I wonder why it failed? Please help....thanks in advance.
 

it turns out to be silly problem....the simulation takes like 1100us to initialize in 3.125G mode, while only 720us in 5G mode
 

That is because the line rate is significantly lower. I imagine the 1100us is probably closer to 1152us....

3.125/5.000 = 720/1152... from what I've seen these transceiver type simulations always scale in initialization time based on the line rate as they all have to synchrnoize to some specific pattern. Something to remember next time you run a simulation on a transceiver design.
 

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