Low speed bank Clock pins

Hi,

I know this question may sound really dumb. However, I do not really get it.
On MAX10 there are high speed and low speed IO pin Banks. Are the clock pin on the low speed banks have less accuracy or is it just the same as the one on High speed IO pins?
Thank you.

Best regards,

RH

No, the "faster" I/Os just use an LVDS electrical standard.
It has a relatively low voltage swing and is also differential - which makes it appropriate to use for high speed signals.

So I can use any clock pin on fpga and all of them will basically the same?

MAX10 high speed low speed pins

Hi,

I have yet another simple questions.
1. I really want to understand what is the difference between high speed and low speed io pins on max10. I tried to look around but cannot find an answer about this. Can anyone help?
2. To send clock signal from MAX10 to another IC such as spi clock signal, should I just use PLL out pins, DPCLK pins or the clock pins will work just fine? The speed of the communication is 5.5MHz which is not really fast I think.
Thank you.

Best regards,

RH

I suggest you read the documentation that Altera provides. I've included the links to the appropriate documents.

1. There are two user guides for the I/O:
The general purpose I/O. This is the single ended I/O standards I'm tool lazy to look through the following to see which specific standards the I/O supports.
https://www.altera.com/documentation/sam1393999966669.html
and the High Speed LVDS I/O. This is a differential standard. And from the name appears to only support LVDS.
https://www.altera.com/documentation/sam1394433606063.html
and the difference (if not already obvious) is that one supports the LVDS standard and the other pin type supports single ended standards.

2. Did you ever read any of the user guides on altera's website?
https://www.altera.com/documentation/mcn1395213337540.html Read the section "Dual-Purpose Clock Pins" and it tells you exactly what those pins are used for. FYI they are not used to output clocks to another device. The section titled "Global Clock Control Block" has a nice diagram of how the clock interface to the GCLK network.


I suggest you look over the following page and most of the documents that are show in the Recommended Documents filter.
https://www.altera.com/products/fpga/max-series/max-10/support.html

1. I really want to understand what is the difference between high speed and low speed io pins on max10. I tried to look around but cannot find an answer about this. Can anyone help?

Click to expand...

As the device manual states, the actual assignment of high and low speed pins can be found in the pinout file. It's also shown in Quartus pin planner tool.

If you look at the device datasheet, you get the impression that the differences between nominal low and high speed pins are marginal and irrelevant for 95 % of applications. Other than stated above in post #2, it's not related to availability of LVDS IO standard in the respective banks. But there may be differences for other IO standards that I didn't yet use in MAX10 designs.

Any IO pin can be used for slow SPI interfaces. A 5.5 MHz SPI clock will be usually a logic generated signal rather than a PLL clock output, thus there's no purpose of using dedicated clock outputs.

As usual thank you very much for giving such a clear answer.

FvM said:

As the device manual states, the actual assignment of high and low speed pins can be found in the pinout file. It's also shown in Quartus pin planner tool.

If you look at the device datasheet, you get the impression that the differences between nominal low and high speed pins are marginal and irrelevant for 95 % of applications. Other than stated above in post #2, it's not related to availability of LVDS IO standard in the respective banks. But there may be differences for other IO standards that I didn't yet use in MAX10 designs.

Any IO pin can be used for slow SPI interfaces. A 5.5 MHz SPI clock will be usually a logic generated signal rather than a PLL clock output, thus there's no purpose of using dedicated clock outputs.

Click to expand...

Hi, you said that 5.5 MHz can be driven by logic generated signal, is there any source for this information or it is just based on your own experience? Thank you.

Hi,

You may generate any clock signal by logic.

The point is that you should not directely use such a signal as internal clock signal.

For internal use: generate enable signals but use the system clock.

Think in hardware:
Imagine a counter having two inputs: CLK and ENA
* connect CLK with your system clock
* generate ENA with logic

Klaus

Hi, you said that 5.5 MHz can be driven by logic generated signal, is there any source for this information or it is just based on your own experience?

Click to expand...

Read the SPI docu carefully.

A master SPI generates the SCLK: Serial Clock (output from master). A 5.5 MHz is relatively slow clock. You master module core clock might be working at a much higher freq. So you write logic inside your SPI core such that a 5.5MHz toggling signal is generated that will be the SCLK.