# how to write a verilog code using point form??

1. ## how to write a verilog code using point form??

parameter RED =3'b000; //if assume as 0 round off ~ 0
parameter YELLOW =3'b001; //if assume as 1.2 round off ~1
parameter GREEN =3'b010; //if assume as 2.1 round off ~ 2
parameter BLUE =3'b011; //if assume as 1.7 round off ~ 2
parameter COKLAT =3'b100; //if assume as 0.2 round off ~ 0
parameter BLACK =3'b101; //if assume as 1.4 round off ~ 1
parameter PURPLE =3'b110; //if assume as 2.4 round off ~ 2
parameter ORANGE =3'b111; //if assume as 0.8 round off ~ 1

i want to make coding which i represent the parameter of 3 bit to a point form integer. after that i want to make a condition if the assume is given then it will trigger to the round off number...

exmple : if i want 3 bit (001) which i assume to be 1.2 will be 1 as output....???plz help me with this coding....??

•

2. ## Re: how to write a verilog code using point form??

Originally Posted by yeppolife92
parameter RED =3'b000; //if assume as 0 round off ~ 0
parameter YELLOW =3'b001; //if assume as 1.2 round off ~1
parameter GREEN =3'b010; //if assume as 2.1 round off ~ 2
parameter BLUE =3'b011; //if assume as 1.7 round off ~ 2
parameter COKLAT =3'b100; //if assume as 0.2 round off ~ 0
parameter BLACK =3'b101; //if assume as 1.4 round off ~ 1
parameter PURPLE =3'b110; //if assume as 2.4 round off ~ 2
parameter ORANGE =3'b111; //if assume as 0.8 round off ~ 1

i want to make coding which i represent the parameter of 3 bit to a point form integer. after that i want to make a condition if the assume is given then it will trigger to the round off number...

exmple : if i want 3 bit (001) which i assume to be 1.2 will be 1 as output....???plz help me with this coding....??
hi,
so basically you need to round your fixed point fractional number to an integer right?

how you represent the fractional number (eg: 1.2) in binary form ?
what is fractional width and integer width ?
how you are giving input to the design ?

regards

3. ## Re: how to write a verilog code using point form??

yeppolife92,

It appears you don't know how fixed point values are represented in binary.

The fixed point numbers are made up of sums of powers of 2.

e.g.
Code:
```Q2.5 would be an 8-bit signed fixed point number with the value in decimal calculated by the following
-s*2**2 + m[1]*2**1 + m[0]*2**0 + f[4]*2**-1 + f[3]*2**-1 + f[2]*2**-1 + f[1]*2**-1 + f[0]*2**-1
or..
-s*4 + m[1]*2 + m[0] + f[4]*0.5 + f[3]*0.25 + f[2]*0.125 + f[1]*0.0625 + f[0]*0.03125

therefore if you have a number like 010.11001 that would become:
-0*4 + 1*2 + 0 + 1*0.5 + 1*0.25 + 0*0.125 + 0*0.0625 + 1*0.03125 = 2.78125```
With your number descriptions of 0-2.4 the best you can achieve with 3-bits is numbers like: 0, 0.5, 1.0, 1.5, etc. as you can only represent fx2.3 (2 magnitude bits with 1 fractional bit...3-bits total) so the magnitude can be 0-3 and the fraction is either 0 or .5.
If the factional part is 1 then round up otherwise truncate.

•

4. ## Re: how to write a verilog code using point form??

im sorry bro...i still cant get it? i still dont know how to write coding in this case..

5. ## how to write a code in point form part 2

hye gaizz,

parameter RED =3'b000; //if assume as 0 round off ~ 0
parameter YELLOW =3'b001; //if assume as 1.2 round off ~1
parameter GREEN =3'b010; //if assume as 2.1 round off ~ 2
parameter BLUE =3'b011; //if assume as 1.7 round off ~ 2
parameter COKLAT =3'b100; //if assume as 0.2 round off ~ 0
parameter BLACK =3'b101; //if assume as 1.4 round off ~ 1
parameter PURPLE =3'b110; //if assume as 2.4 round off ~ 2
parameter ORANGE =3'b111; //if assume as 0.8 round off ~ 1

i want to make coding which i represent the parameter of 3 bit to a point form integer. after that i want to make a condition if the assume is given then it will trigger to the round off number...

exmple : if i want 3 bit (001) which i assume to be 1.2 will be 1 as output....???plz help me with this coding....??

//below is the coding that i have done..the above description is the question i ask for upgrading the coding below..can u help me?

[syntax=verilog]module decoder(
input wire CLK,
input wire RESET,
output reg[2:0]A,
output[6:0]state,
output reg[6:0]count
);

reg[6:0]decoder_state;
reg[6:0]step;

//output declaration

parameter RED =3'b000;
parameter YELLOW =3'b001;
parameter GREEN =3'b010;
parameter BLUE =3'b011;
parameter COKLAT =3'b100;
parameter BLACK =3'b101;
parameter PURPLE =3'b110;
parameter ORANGE =3'b111;

//state

parameter S0=7'b0000000,

S1 =7'b0000001,

S2 =7'b0000011,

S3 =7'b0000111,

S4 =7'b0001111,

S5 =7'b0011111,

S6 =7'b0111111,

S7 =7'b1111111,

S8 =7'b1111110,

S9 =7'b1111100,

S10 =7'b1111000,

S11 =7'b1110000,

S12 =7'b1100000,

S13 =7'b1000000,

S14 =7'b0000000,

S15 =7'b0001000,

S16 =7'b0011000,

S17 =7'b0001110,

S18 =7'b0111100,

S19 =7'b0111110,

S20 =7'b1110111,

S21 =7'b1111111,

S22 =7'b1011111,

S23 =7'b1001111,

S24 =7'b0011110,

S25 =7'b0011100,

S26 =7'b0001100,

S27 =7'b0010000,

S28 =7'b0000000;

//COUNT

parameter SEC13 =7'b0001101;

parameter SEC7 =7'b0000111;

assign state=decoder_state;

always@(posedge CLK or posedge RESET)

begin

if(RESET==1)

begin
decoder_state<=S0;
count<=0;
end

else

case(step)
0: if(count<SEC13)
begin
step<=0;
decoder_state<=S0;
count<=count+1'b1;
end
else
begin
step<=1;
decoder_state<=S1;
count<=0;
end

1: if(count<SEC7)
begin
step<=1;
decoder_state<=S1;
count<=count+1'b1;
end
else
begin
step<=2;
decoder_state<=S2;
count<=0;
end

2: if(count<SEC7)
begin
step<=2;
decoder_state<=S2;
count<=count+1'b1;
end
else
begin
step<=3;
decoder_state<=S3;
count<=0;
end

3: if(count<SEC7)
begin
step<=3;
decoder_state<=S3;
count<=count+1'b1;
end
else
begin
step<=4;
decoder_state<=S4;
count<=0;
end

4: if(count<SEC7)
begin
step<=4;
decoder_state<=S4;
count<=count+1'b1;
end
else
begin
step<=5;
decoder_state<=S5;
count<=0;
end

5: if(count<SEC7)
begin
step<=5;
decoder_state<=S5;
count<=count+1'b1;
end
else
begin
step<=6;
decoder_state<=S6;
count<=0;
end

6: if(count<SEC7)
begin
step<=6;
decoder_state<=S6;
count<=count+1'b1;
end
else
begin
step<=7;
decoder_state<=S7;
count<=0;
end

7: if(count<SEC13)
begin
step<=7;
decoder_state<=S7;
count<=count+1'b1;
end
else
begin
step<=8;
decoder_state<=S8;
count<=0;
end

8: if(count<SEC7)
begin
step<=8;
decoder_state<=S8;
count<=count+1'b1;
end
else
begin
step<=9;
decoder_state<=S9;
count<=0;
end

9: if(count<SEC7)
begin
step<=9;
decoder_state<=S9;
count<=count+1'b1;
end
else
begin
step<=10;
decoder_state<=S10;
count<=0;
end

10: if(count<SEC7)
begin
step<=10;
decoder_state<=S10;
count<=count+1'b1;
end
else
begin
step<=11;
decoder_state<=S11;
count<=0;
end

11: if(count<SEC7)
begin
step<=11;
decoder_state<=S11;
count<=count+1'b1;
end
else
begin
step<=12;
decoder_state<=S12;
count<=0;
end

12: if(count<SEC7)
begin
step<=12;
decoder_state<=S12;
count<=count+1'b1;
end
else
begin
step<=13;
decoder_state<=S13;
count<=0;
end
13: if(count<SEC7)
begin
step<=13;
decoder_state<=S13;
count<=count+1'b1;
end
else
begin
step<=14;
decoder_state<=S14;
count<=0;
end

14: if(count<SEC13)
begin
step<=14;
decoder_state<=S14;
count<=count+1'b1;
end
else
begin
step<=15;
decoder_state<=S15;
count<=0;
end

15: if(count<SEC7)
begin
step<=15;
decoder_state<=S15;
count<=count+1'b1;
end
else
begin
step<=16;
decoder_state<=S16;
count<=0;
end

16: if(count<SEC7)
begin
step<=16;
decoder_state<=S16;
count<=count+1'b1;
end
else
begin
step<=17;
decoder_state<=S17;
count<=0;
end

17: if(count<SEC7)
begin
step<=17;
decoder_state<=S17;
count<=count+1'b1;
end
else
begin
step<=18;
decoder_state<=S18;
count<=0;
end

18: if(count<SEC7)
begin
step<=18;
decoder_state<=S18;
count<=count+1'b1;
end
else
begin
step<=19;
decoder_state<=S19;
count<=0;
end

19: if(count<SEC7)
begin
step<=19;
decoder_state<=S19;
count<=count+1'b1;
end
else
begin
step<=20;
decoder_state<=S20;
count<=0;
end

20: if(count<SEC7)
begin
step<=20;
decoder_state<=S20;
count<=count+1'b1;
end
else
begin
step<=21;
decoder_state<=S21;
count<=0;
end

21: if(count<SEC13)
begin
step<=21;
decoder_state<=S21;
count<=count+1'b1;
end
else
begin
step<=22;
decoder_state<=S22;
count<=0;
end

22: if(count<SEC7)
begin
step<=22;
decoder_state<=S22;
count<=count+1'b1;
end
else
begin
step<=23;
decoder_state<=S23;
count<=0;
end

23: if(count<SEC7)
begin
step<=23;
decoder_state<=S23;
count<=count+1'b1;
end
else
begin
step<=24;
decoder_state<=S24;
count<=0;
end

24: if(count<SEC7)
begin
step<=24;
decoder_state<=S24;
count<=count+1'b1;
end
else
begin
step<=25;
decoder_state<=S25;
count<=0;
end

25: if(count<SEC7)
begin
step<=25;
decoder_state<=S25;
count<=count+1'b1;
end
else
begin
step<=26;
decoder_state<=S26;
count<=0;
end

26: if(count<SEC7)
begin
step<=26;
decoder_state<=S26;
count<=count+1'b1;
end
else
begin
step<=27;
decoder_state<=S27;
count<=0;
end

27: if(count<SEC7)
begin
step<=27;
decoder_state<=S27;
count<=count+1'b1;
end
else
begin
step<=28;
decoder_state<=S28;
count<=0;
end

28: if(count<SEC13)
begin
step<=28;
decoder_state<=S28;
count<=count+1'b1;
end

else
begin
decoder_state<=S0;
count<=0;
end
default: decoder_state<=S0;
endcase
end

always@(*)

begin
case(decoder_state)

S0: begin
A=RED;
end

S1: begin
A=YELLOW;
end

S2: begin
A=GREEN;
end

S3: begin
A=BLUE;
end

S4: begin
A=COKLAT;
end

S5: begin
A=BLACK;
end

S6: begin
A=PURPLE;
end

S7: begin
A=ORANGE;
end

S8: begin
A=PURPLE;
end

S9: begin
A=BLACK;
end

S10: begin
A=COKLAT;
end

S11: begin
A=BLUE;
end

S12: begin
A=GREEN;
end

S13: begin
A=YELLOW;
end

S14: begin
A=RED;
end

S15: begin
A=YELLOW;
end

S16: begin
A=GREEN;
end

S17: begin
A=BLUE;
end

S18: begin
A=COKLAT;
end

S19: begin
A=BLACK;
end

S20: begin
A=PURPLE;
end

S21: begin
A=ORANGE;
end

S22: begin
A=PURPLE;
end

S23: begin
A=BLACK;
end

S24: begin
A=COKLAT;
end

S25: begin
A=BLUE;
end

S26: begin
A=GREEN;
end

S27: begin
A=YELLOW;
end

S28: begin
A=RED;
end

default: begin
A=RED;
end
endcase
end
endmodule[/syntax]

6. ## Re: how to write a verilog code using point form??

yup..and i want the coding of that..

•

7. ## Re: how to write a verilog code using point form??

Originally Posted by yeppolife92
yup..and i want the coding of that..
hi ,

i assume you didnt done tthe coding for this::
exmple : if i want 3 bit (001) which i assume to be 1.2 will be 1 as output....???plz help me with this coding....??

//below is the coding that i have done..the above description is the question i ask for upgrading the coding below..can u help me?
.................................................. .............................
parameter RED =3'b000; //if assume as 0 round off ~ 0
parameter YELLOW =3'b001; //if assume as 1.2 round off ~1
parameter GREEN =3'b010; //if assume as 2.1 round off ~ 2
parameter BLUE =3'b011; //if assume as 1.7 round off ~ 2
parameter COKLAT =3'b100; //if assume as 0.2 round off ~ 0
parameter BLACK =3'b101; //if assume as 1.4 round off ~ 1
parameter PURPLE =3'b110; //if assume as 2.4 round off ~ 2
parameter ORANGE =3'b111; //if assume as 0.8 round off ~ 1
based on above statements max value is 2.4 . so if you take an 8 bit binary ( two bit for integer & 6 bit for fraction)
10.011001 = 2.390625 ( 2^1*1+2^0*0 . 0*2^-1+1*2^-2+1*2^-3...)
== 2+0 . (0+.25+.125+0+0.015625)=2.390625
so with a 3 bit binary, max you can achieve is .5 accuracy . (01.1)=(2.5)

please check ads-ee replay above . he explain this better . i think if you get some clarity on how to represent a fractional number you can easily solve this.
because in your coding you need to decide how many integer & fractional width you need to use based on your requirements :)

its based on you for 2.4 ,either you need to use 8 bit 10.011001 = 2.390625 or 16bit 10.01100110011001=2.39996337890625

parameter BLUE =3'b011; //if assume as 1.7 round off ~ 2
so please decide the fixed and integer width ( i am taking here 8 bit )

01.101100 =1.6875 thats max you can achieve using 8 width.
01.100000 = 1.5

x = 8'b01101100;
if ( 8'b01100000 < x) begin

y<= 3'b010;

end else begin

y <= 3'b001;

end

regards

8. ## Re: how to write a verilog code using point form??

3-bits cannot represent numbers like 1.7 etc.

all possible numbers in a fx2.3 (positive only - 2 integer and 3 total bits, i.e. 2 integer and 1 fractional bit) representation:
Code:
```000 - 0.0
001 - 0.5
010 - 1.0
011 - 1.5
100 - 2.0
101 - 2.5
110 - 3.0
111 - 3.5```
as you can see the bit width of 3 is limiting the values you can represent. So you will have to increase the bit width of the fractional part of your values, as dipin mentioned, or settle with the above fixed point numbers.

Instead of trying to make these numbers from this list be fractional values I suggest you just make them a look up table.
[syntax=verilog]reg [1:0] round_off;
case (color)
RED : round_off <= 0;
YELLOW : round_off <= 1;
GREEN : round_off <= 2;
BLUE : round_off <= 2;
COKLAT : round_off <= 0;
BLACK : round_off <= 1;
PURPLE : round_off <= 2;
ORANGE : round_off <= 1;
endcase[/syntax]
Seems a lot easier this way to me, than trying to fit this non-linear arrangement of values into integers.

I really think you should step back and look at the overall problem and the solution, I don't think you understand what you are doing at this point. Don't you have some sort of experienced mentor that can assist you with ideas of how to approach whatever it is you are attempting to do?

- - - Updated - - -

FYI: edaboard isn't a suitable substitution for a university instructor or an experienced mentor.

--[[ ]]--