shaiko
Advanced Member level 5
Hello,
Signal_X in an input pin to my FPGA.
Signal_X is synchronous to clock_x which is also an input pin.
clock_x drives a pll input and becomes pll_clock_x.
pll_clock_x is phase aligned to clock_x and is used to latch signal_x.
Question:
When constraining signal_x for input_delay - what clock should be used? Clock_x or pll_clock_x ?
Signal_X in an input pin to my FPGA.
Signal_X is synchronous to clock_x which is also an input pin.
clock_x drives a pll input and becomes pll_clock_x.
pll_clock_x is phase aligned to clock_x and is used to latch signal_x.
Question:
When constraining signal_x for input_delay - what clock should be used? Clock_x or pll_clock_x ?