Will long inverter chains cause duty cycle distortion?

I have been recently working on a PAM4 transmitter with its output having duty cycle distortion.In theory,its duty-cycle accords with the high-frequency clock's generating it.Since that clock only comes from an external clock going through a CML2CMOS converter and a series of CMOS buffers(over 20 stages),what could possibly go wrong?

Yes, they can - especially if you have nonuniform taper
progression. The rise / fall edge time asymmetry can
stack up (and is very loading-detail-sensitive; slow
edges are where you convert voltage noise (as can
be seen on your top trace) to time noise (jitter)).

I once had to redo a chip-scale clock tree (on a
40Kgate ASIC done by Spectre simulation and hand
layout of every steenkin' gate and upward) because
I encountered this kind of distortion, having used
buffer gates (noninverting) with 1X:3X inverters.
The internal node was fast and the external was
slow, and the difference really stacked up over the
tree depth. Noninverting stages do that while matched
inverting stages first-order cancel. You want to look
at the edge rate of each inverter stage and try to
keep them matched inclusive of the true net loading.

Now, you might also suffer from wafer processing
skew (N vs P drive strength and inverter net threshold).
Expect the lvt devices to vary more widely than regular
(lighter implants are more sensitive to gate ox / channel
surface qualities, random dopant fluctuation, etc. in VT
and drive strength).

That's something you could explore in Spectre. But I'd
explore it using an analog_extracted netlist of high
(relative to final layout) parasitics fidelity, schematic
based simulation is likely to miss the mark.

Every AND Gate will bring some intrinsic capacitance and this will lead to increase the Rise Time and Fall Time.And this is sequential so it's added gate by gate.

Not exactly true. The rise/fall time depends on taper
factor and wire loads in a given technology. Tr/Tf will
reach an asymptote at some point (chain-length) if
taper factor remains constant (and loading, proportional
to drive strength).

But if a consistent (and unidirectional) delay skew
exists at each stage, that -will- accumulate. An AND
gate is noninverting so a chain of ANDs will accumulate
a duty cycle distortion. A chain of NANDs (given a
uniform loading / taper) will cancel duty cycle distortion
to first order.

dick_freebird said:

Yes, they can - especially if you have nonuniform taper
progression. The rise / fall edge time asymmetry can
stack up (and is very loading-detail-sensitive; slow
edges are where you convert voltage noise (as can
be seen on your top trace) to time noise (jitter)).

I once had to redo a chip-scale clock tree (on a
40Kgate ASIC done by Spectre simulation and hand
layout of every steenkin' gate and upward) because
I encountered this kind of distortion, having used
buffer gates (noninverting) with 1X:3X inverters.
The internal node was fast and the external was
slow, and the difference really stacked up over the
tree depth. Noninverting stages do that while matched
inverting stages first-order cancel. You want to look
at the edge rate of each inverter stage and try to
keep them matched inclusive of the true net loading.

Now, you might also suffer from wafer processing
skew (N vs P drive strength and inverter net threshold).
Expect the lvt devices to vary more widely than regular
(lighter implants are more sensitive to gate ox / channel
surface qualities, random dopant fluctuation, etc. in VT
and drive strength).

That's something you could explore in Spectre. But I'd
explore it using an analog_extracted netlist of high
(relative to final layout) parasitics fidelity, schematic
based simulation is likely to miss the mark.

Click to expand...

1)Can those rise/fall edges be so asymmetrical now that I've keep the N ratio relatively reasonable?And from Spectre,the edge-rate seems perfectly matched.Also,I can understand the problem if the chain is single-ended,but these are differential clocks between which I put some cross-coupled inverters.At least I can't see any duty cycle distortion on Spectre level.Maybe you can give me more clue on the analog_extracted netlist?
2)What is this taper factor all about?Is it something like fanout?
3)I think fast-edges can also turn voltage noise into jitter,only smaller than the slow-ones'.

All edges transform voltage noise to time. Slower
makes more time jitter per voltage amplitude.

Taper factor is not fanout per se, but the ratio of
driven to driving stage in the buffer chain itself. A
fanout effect is there but so is drive-current gain
(loguc fanout generally, is just loading as the outputs
do not sum, but diverge to different destinations).
Folk wisdom is that a 1:3 taper gives the minimum
delay on a long chain (less taper = more stages to
get desired end-point current drive; more taper per
stage means less stages but slower edge rates and
stage delay includes at least half of the rise time).

Rise fall symmetry can be dialed in for one process
point (like TT) but at other places a skew (in either
direction) may develop. I design clock trees at SS
corner (if "digital" models is all I've been given) with
the idea that anywhere else would be better, but a
FS or SF corner might be worse for things where
duty cycle rather than setup time is the main concern.

Cross coupled inverters can sharpen the edge through
the transition / linear region, but may add delay as
the driving stage has to fight before anything at all
happens. Might put the bare vs cross-coupled up
against each other in simulation and see if this is
part of the problem, contributes to rather than
heals rise/fall time asymmetry (as again you will be
making a N vs P head-butting contest, process
skews may enter into it here; also the scaling of
the XC loads vs the driver matters I think).