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Using Synopsys DC, power report problem

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minho_ha

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I'm trying to get power consumption report using Synopsys DC.

When I compiled my verilog file before, power report was fine.

But, today, I compiled same verilog file again, power report is strange. Switching power accounts for more than 95% of dynamic power. Before that, the switching power was about 30% of the dynamic power.

Can you guess where is the problem??

I'm not familiar with using synopsys DC. (I'm familiar with FPGA)

Please help.
 

Very difficult for someone else to say.
Try to find out what parameters have changed since your previous run.
 
You probably have made some changes to your verilog file. Be aware that power report generated by Design Compiler is not accurate as it only uses estimated switching activity.
 
inputoutput said:
You probably have made some changes to your verilog file. Be aware that power report generated by Design Compiler is not accurate as it only uses estimated switching activity.
Click to expand...

it can be made accurate, or as accurate as you can get during synthesis
 

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