# Native VHDL negation function

1. ## Native VHDL negation function

Hello,

Does VHDL have a native 2's complement negation function for signed vectors ?
I.E - a function that takes a signed vector, flips it and adds '1' to the LSB ?

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2. ## Re: Native VHDL negation function

yes:

a <= -b;

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3. ## Re: Native VHDL negation function

Originally Posted by TrickyDicky
yes:

a <= -b;
I'm guessing the types for a and b should be signed from numeric_std?

4. ## Re: Native VHDL negation function

Originally Posted by ads-ee
I'm guessing the types for a and b should be signed from numeric_std?
I know that you might think of std_logic_signed, std_logic_arith, but no one should use them, instead, the standard.

-- Id: A.2
function "-" (ARG: SIGNED) return SIGNED;
-- Result subtype: SIGNED(ARG'LENGTH-1 downto 0).
-- Result: Returns the value of the unary minus operation on a
-- SIGNED vector ARG.

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5. ## Re: Native VHDL negation function

Originally Posted by ads-ee
I'm guessing the types for a and b should be signed from numeric_std?
Yes - any standard signed type will work:
integer
real

And from VHDL 2008
sfixed
std_logic_vector (when using numeric_std_signed)
bit_vector (when using numeric_bit_signed)

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6. ## Re: Native VHDL negation function

Originally Posted by TrickyDicky
Yes - any standard signed type will work:
integer
real
If my understanding is correct, real isn't synthesizable, and integer isn't really a good fit if you want to synthesize something with a fixed bit with that is less than or more than the definition of integer (usually 32-bits in most implementations) and will require extra conversions to make it the correct size. I suppose you can specify a range, but then I always have to mentally convert the range to number of bits in the vector.

Originally Posted by TrickyDicky
And from VHDL 2008
sfixed
std_logic_vector (when using numeric_std_signed)
bit_vector (when using numeric_bit_signed)
I sort of knew about sfixed, but the numeric_std_signed and _bit_signed seem to be addressing the non-IEEE standard package std_logic_signed? I find this very interesting. So is using these packages to allow the use of std_logic_vector (e.g. like a std_logic_vector slice) as part of a signed calculation? That would be convenient and would require less conversions.

7. ## Re: Native VHDL negation function

I don't think real has an explicit definition in VHDL in terms of binary representation.

I'll also note that you can import only numeric_std_signed."-" or std_logic_signed."-" . This is advisable as using the entire package changes "=" . For std_logic_1164, comparing different widths for equality would generate an easy to find warning "result always false". For numeric_std_signed, they would each be treated as signed numbers and compared in that manner. "11" = "111".

That would be convenient and would require less conversions.
IMO, this is a big reason why std_logic_unsigned still exists. It makes VHDL more like Verilog, especially if you include conv_integer from std_logic_arith. (this is "to_integer" in numeric_std_unsigned). I still don't advocate using all of either due to the changes to "=", and because I feel there is value in using signed/unsigned type when there is ambiguity in the operation.

8. ## Re: Native VHDL negation function

Originally Posted by vGoodtimes
I'll also note that you can import only numeric_std_signed."-" or std_logic_signed."-" . This is advisable as using the entire package changes "=" . For std_logic_1164, comparing different widths for equality would generate an easy to find warning "result always false". For numeric_std_signed, they would each be treated as signed numbers and compared in that manner. "11" = "111".
I think you mean - IMO, you SHOULD only import numeric_std_signed or std_logic_signed. This is only an opinion, and I doubt anyone will really follow it - importing the whole package is just easier. Also, with a lack of decent VHDL 2008 until rather recently, you're unlikely to see any coding standards mention numeric_std_signed/unsigned at all - most will advocate using numeric_std.
std_logic_1164 does not define any "=" functions. "=" is declared implicitly for all types in the language. Otherwise you would get a conflict when you imported std_logic_unsigned or numeric_std_signed etc and you would have to chose which one to use explicitly (as you kind of alluded to).

@ads-ee : I wasnt really talking in terms of synthesis, I was just listing all standard types where the function "-" function is defined.

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9. ## Re: Native VHDL negation function

I think we agree, but am not sure. My opinion is that the smallest, easily understood subset of _signed/_unsigned/etc... be used in a design. This is "+" from either signed/unsigned, "-" from signed, and to_integer from unsigned or conv_integer from std_logic_arith (or if you hate the non-ieee of the package, "to_int" from your own package.)

"-" from _signed is to add the unary operator.

This gives convenience without redefining a useful property of "=", nor making ambiguous inequalities or multiplications seem like a good idea.

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