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The error about ARAM reading

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Kynix

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Good afternoon~:-DI'm coming again! Thank you for taking time to read my thread.Today I'm also confusing about the FPGA. I hope someone in the forum can help me.:???:
I would like to ask the question about the reading of ARAM.
Please look at the following picture,when addr is 2, the dout should be 3.Why it appeared 1 here?
BRAM program.pngBRAM simulation.pngthe picture of BRAM simulation.png

Your help will be appreciated!
Wishes~:)
 

All BRAMs are synchronous, hence you get the data 1 clock after the address. ARAMs in FPGAs have to be built from logic and have low performance.
 

TrickyDicky said:
All BRAMs are synchronous, hence you get the data 1 clock after the address. ARAMs in FPGAs have to be built from logic and have low performance.
Click to expand...

So...what do you mean? Can you explain it more clearly?
 

There are no asynchronous RAMs in an FPGA is that clear enough?

If you try to implement one it will either a) fail to implement, or b) end up as a huge design that implements latches in the LUT fabric to store bits.
 

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