NikosTS
Advanced Member level 4
I am trying to design a 3rd order SD modulator ( MASH 1-1-1 topology ), but with reduced hardware. That means, that only the first accumulator will have full length ( N ) and the other two accumulators will have reduced lengths ( L < M < N ).
According to the literature, in order to get the maximum sequence length, we set the LSB of the input to "1". This results to the input being odd always ( and sequence 2^N for first-order modulator is guaranteed).
But what if we need an even input? We still have to set the LSB to "1"? And if that's the case, does that mean that i will only get an estimation of my desired fractional word?
Thank you in advance,
Nikos
According to the literature, in order to get the maximum sequence length, we set the LSB of the input to "1". This results to the input being odd always ( and sequence 2^N for first-order modulator is guaranteed).
But what if we need an even input? We still have to set the LSB to "1"? And if that's the case, does that mean that i will only get an estimation of my desired fractional word?
Thank you in advance,
Nikos