msdarvishi
Full Member level 4
Dear all,
I am using Vivado 2016.1 and I would like to do the routing between two logic resources located in different slices and CLBs. I know that this routing must pass through different switch matrixes and logic resources and I know it is possible to do it via constraints definition. I have read UG894 and UG895 but they are so extensive and complicated ! Can anybody provide me a simple example of routing between two flip-flops to extend it for my own purpose?
P.S. : Previously this task was feasible in ISE FPGA Editor by Manual routing and I know it is possible in Vivado using scripts.
Kind replies are in advance appreciated.
Thanks,
I am using Vivado 2016.1 and I would like to do the routing between two logic resources located in different slices and CLBs. I know that this routing must pass through different switch matrixes and logic resources and I know it is possible to do it via constraints definition. I have read UG894 and UG895 but they are so extensive and complicated ! Can anybody provide me a simple example of routing between two flip-flops to extend it for my own purpose?
P.S. : Previously this task was feasible in ISE FPGA Editor by Manual routing and I know it is possible in Vivado using scripts.
Kind replies are in advance appreciated.
Thanks,