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fir filter output verification

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dipin

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fir filter decimation using verilog

hi,

i need to down sample a 10 khz digital inputs to 200 hz using fir filter.
so decimation rate is 50 (10khz/200 hz). i think there is two ways to do it:::

1) select every 50th sample & multiply it with filter coefficients

2) multiply every sample with filter coefficient & take only 50 th output every time..

i am decided to implement the decimation using a counter ..
i know 1st method is good because of reduced multiplication & addition.. but if i do so,, is it right??

did anybody can give a suggestion about this??
(( i am using a 20 tap fir filter which coefficients generated from math_lab))

thanks and regards
 

Re: fir filter decimation using verilog

Method 1 (simple undersampling) will mirror noise and unwanted signal above the Nyquist frequency of 100 Hz into the base band. Unless the input signal is already band limited, you need to low-pass filter before down sampling.

A 20 tap FIR can't achieve a cut-off frequency of 0.01 fs as required for effective implementation of method 2.

In practice, you'll at least average the samples, implementing a first order CIC. It's sin(x)/x characteristic achieves a moderate reduction of out-of-band noise and interferences.
 
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Re: fir filter decimation using verilog

Hi,

The first solution needs less processing power. But it doesn´t take care about frequencies from 100Hz....5kHz (both sample rate nyquist frequencies).
So if the original (10k sample/s) source includes frequecies in that range they will produce alias frequencies in the range of 0..100Hz.

Therefore I´d prefer solution2
And within an FPGA a little FIR or IIR filter is about "no" processing power.

Klaus

Read about: IIR filter, biquad... = really low processing power, but very flexible.
 
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Re: fir filter decimation using verilog

Method 1 (simple undersampling) will mirror noise and unwanted signal above the Nyquist frequency of 100 Hz into the base band. Unless the input signal is already band limited, you need to low-pass filter before down sampling.

In practice, you'll at least average the samples, implementing a first order CIC. It's sin(x)/x characteristic achieves a moderate reduction of out-of-band noise and interferences.

thanks for the replay fvm,

my 10khz input is coming from a cic filter... which is convert 65mhz to 10 khz by 3 stages.. (thats a lots of down sampling !!!)

A 20 tap FIR can't achieve a cut-off frequency of 0.01 fs as required for effective implementation of method 2.
how we will know that it wont work effectively ? can you please give some information about this?

regards

- - - Updated - - -

Hi,

The first solution needs less processing power. But it doesn´t take care about frequencies from 100Hz....5kHz (both sample rate nyquist frequencies).
So if the original (10k sample/s) source includes frequecies in that range they will produce alias frequencies in the range of 0..100Hz.

Therefore I´d prefer solution2
And within an FPGA a little FIR or IIR filter is about "no" processing power.

Klaus

Read about: IIR filter, biquad... = really low processing power, but very flexible.

hi klaussat,
i didnt clearly got what you said above... but sure i will read it try to understand. thanks for the replay .

regards
 

Re: fir filter decimation using verilog

Hi,

i didnt clearly got what you said above
.. about the same as FvM.

The low pass filter (anti-alias) shouldn´t be the problem in FPGAs.

Klaus
 
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Re: fir filter decimation using verilog

how we will know that it wont work effectively ?
By simulating the filter frequency response.

Problem is you didn't tell any requirements for the decimator like frequency response, acceptable delay.
 
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Re: fir filter decimation using verilog

By simulating the filter frequency response.

Problem is you didn't tell any requirements for the decimator like frequency response, acceptable delay.

hi FvM,

They didnt told anything related to the design except " get a 200 hz output from a 10khz input coming from a cic filter". i think everything else must decide by me.
i saw few fir example they all have initial parameters like pass band frequency,pass band ripple, stopband frequency, stopband ripple..from that we can determine filter length..this is the point i am stuck with :(

and based on your post 1, method 1 is a bad idea ..so i must go for method 2 with proper filter length right? ( i will be implementing this using verillog)

regards
 
Last edited:

Re: fir filter decimation using verilog

hi guys,

instead of designing, i generated a fir2 ip in quartus...which will generate filter coefficients,, and i am using same coefficients in my design...the generated design contains 36taps :)
hopes that will work fine.these are the filter coefficients generated
Code:
            CASE (u0_m0_wo0_ca0_q) IS
                WHEN "000000" => u0_m0_wo0_cm0_q <= "0000100100";
                WHEN "000001" => u0_m0_wo0_cm0_q <= "0000011011";
                WHEN "000010" => u0_m0_wo0_cm0_q <= "0000000000";
                WHEN "000011" => u0_m0_wo0_cm0_q <= "1111100010";
                WHEN "000100" => u0_m0_wo0_cm0_q <= "1111010010";
                WHEN "000101" => u0_m0_wo0_cm0_q <= "1111011101";
                WHEN "000110" => u0_m0_wo0_cm0_q <= "0000000000";
                WHEN "000111" => u0_m0_wo0_cm0_q <= "0000101001";
                WHEN "001000" => u0_m0_wo0_cm0_q <= "0001000001";
                WHEN "001001" => u0_m0_wo0_cm0_q <= "0000110011";
                WHEN "001010" => u0_m0_wo0_cm0_q <= "0000000000";
                WHEN "001011" => u0_m0_wo0_cm0_q <= "1110111111";
                WHEN "001100" => u0_m0_wo0_cm0_q <= "1110010100";
                WHEN "001101" => u0_m0_wo0_cm0_q <= "1110100100";
                WHEN "001110" => u0_m0_wo0_cm0_q <= "0000000000";
                WHEN "001111" => u0_m0_wo0_cm0_q <= "0010011001";
                WHEN "010000" => u0_m0_wo0_cm0_q <= "0101000101";
                WHEN "010001" => u0_m0_wo0_cm0_q <= "0111001100";
                WHEN "010010" => u0_m0_wo0_cm0_q <= "0111111111";
                WHEN "010011" => u0_m0_wo0_cm0_q <= "0111001100";
                WHEN "010100" => u0_m0_wo0_cm0_q <= "0101000101";
                WHEN "010101" => u0_m0_wo0_cm0_q <= "0010011001";
                WHEN "010110" => u0_m0_wo0_cm0_q <= "0000000000";
                WHEN "010111" => u0_m0_wo0_cm0_q <= "1110100100";
                WHEN "011000" => u0_m0_wo0_cm0_q <= "1110010100";
                WHEN "011001" => u0_m0_wo0_cm0_q <= "1110111111";
                WHEN "011010" => u0_m0_wo0_cm0_q <= "0000000000";
                WHEN "011011" => u0_m0_wo0_cm0_q <= "0000110011";
                WHEN "011100" => u0_m0_wo0_cm0_q <= "0001000001";
                WHEN "011101" => u0_m0_wo0_cm0_q <= "0000101001";
                WHEN "011110" => u0_m0_wo0_cm0_q <= "0000000000";
                WHEN "011111" => u0_m0_wo0_cm0_q <= "1111011101";
                WHEN "100000" => u0_m0_wo0_cm0_q <= "1111010010";
                WHEN "100001" => u0_m0_wo0_cm0_q <= "1111100010";
                WHEN "100010" => u0_m0_wo0_cm0_q <= "0000000000";
                WHEN "100011" => u0_m0_wo0_cm0_q <= "0000011011";
                WHEN "100100" => u0_m0_wo0_cm0_q <= "0000100100";
                WHEN OTHERS => -- unreachable
                               u0_m0_wo0_cm0_q <= (others => '-');
            END CASE;

it will works fine to generate 200hz from 10khz right??

regards
 

hi,

i had designed a fir filter which will decimate the input by a factor of 50. input samples come at a rate of 10khz & design is also runs at 10khz.

i had generated coefficients from math lab fdatool . its low pass filter , with fs=20000hz,fpass=2500hz & fstop=3000hz. Apass=1 and Astop=80 db.The order is 101(generated by mathlab).when i stimulated in quartus using verilog output is::



input & cofficent width is 16 and i am using a step size of 100 for the input counter. is the output supposed to be like above??
if not, what is the out from a low passs fir filter?how should i verify it ?
any help is really appreciated..

please excuse me if this is stupid question :(
( the frequency of ramp wave form is about 3.8 hz & width of register which all addition and multiplication take place is 38)

Thanks and Regards
 

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The numbers in your post don't fit the wave picture. If the ramp frequency is 3.8 Hz, the filter output rate would be around 50 Hz. But 10 kHz/50 should be 200. Unfortunately the time line is cut.
 

Hi,

I don´t understand what you want to achieve...

input samples come at a rate of 10khz & design is also runs at 10khz.
How does this fit to
fs=20000hz

****
With 10kHz sample rate I´d expect a max signal frequency of 5000Hz (Nyquist)
If you decimate by a factor of 50...
I expect an output rate of 10000Hz / 50 = 200Hz

With 200Hz
I expect an output signal frequency of max. 100Hz. (Nyquist)
Therefore I´d expect an upper cutoff frequency below 100Hz.

***
Are you doing some "undersampling" data processing?
With dedicated frequency shift?

***
Btw: a ramp function contains infinite high frequency components. Even if you use an analog anti alias filter in front of the ADC you will see a distorted ramp in the digital data.


Klaus
 

You actually don't need to filter before decimating. The two operations can be combined. The result is that each tap of the filter is given every Nth input, where N is the decimation rate. For example, if the filter coeff's are 1 2 3 4 5, and you decimate by two:
output 1 is generated from samples 1 to 5. the first tap gets sample 1.
output 2 is generated from samples 3 to 7. the first tap gets sample 3.
there is no reason to compute an output for the 2 to 6 case. That would occur in the filter than decimate case.

The IP might have this as an option already.

A ramp is one possible test signal as an input. you can test this in a testbench. impulses that repeat at a rate longer than, and coprime to the filter length are also good. the output of the filter becomes exactly one of the coefficients (possibly scaled) of the filter. testing with a similar input that is the absolute value of the filter coeff is useful if you want to ensure the output doesn't overflow.
 

hi thanks for the replay everyone,

i think here is some misunderstanding for me :(

below shows two wave forms which one is literal & another is in analog domain..


my data rate is good..i am getting new sample at each 200hz,
but what i am asking is the analog waveform is correct for my filter....
(what exactly fir filter do to the rap wave form, did it change the shape of ramp wave form or increase the frequency of ramp.
currently its frequency is 1.798 hz.. & the output is also same. so my real question is is the period(1/f) of output ramp should be same
or it must vary ??)

previously i done a cic filter (65mhz to 10khz) which will cut all the frequency above 10 khz. if i give any ramp waveform of above 10khz the output will be a stright line . so the fir behavior is same?? 10k to 2.5, it must cut all the frequency above 2.5khz ramp???

any help is really appreciated.the input to fir is from cic filter.

thanks
 

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  • eda2.JPG
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