dzafar
Member level 4
I have three question!
Q1. Say:
signal X, Y: std_logic_vector (7 downto 0);
variable change_bit: std_logic;
change_bit = '0';
X <= "11100110";
Y <= X;
Y(6) <= change_bit; -- Is this valid? i.e. does Y now equal "10100110"?
Q2. Can we initialize an array using pre-defined attributes?
Say:
signal X: std_logic_vector (7 downto 0);
signal Y: X' range; -- is this valid? i.e. does this initialize Y to be (7 downto 0)?
Q3. What happens when:
signal X: std_logic_vector (7 downto 0);
signal X: std_logic_vector (3 downto 0);?
Q1. Say:
signal X, Y: std_logic_vector (7 downto 0);
variable change_bit: std_logic;
change_bit = '0';
X <= "11100110";
Y <= X;
Y(6) <= change_bit; -- Is this valid? i.e. does Y now equal "10100110"?
Q2. Can we initialize an array using pre-defined attributes?
Say:
signal X: std_logic_vector (7 downto 0);
signal Y: X' range; -- is this valid? i.e. does this initialize Y to be (7 downto 0)?
Q3. What happens when:
signal X: std_logic_vector (7 downto 0);
signal X: std_logic_vector (3 downto 0);?