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Is the prefix sum operator synthesizable in verilog??

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kaushikrvs

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Is the prefix sum operator synthesizable in verilog??
 

Yes, however directly inferring prefix-sum may not result in an optimal implementation in terms of area/delay. prefix sum also can be a complex operation. It may be desirable to pipeline the design, or to share adder resources.
 

Yes, however directly inferring prefix-sum may not result in an optimal implementation in terms of area/delay. prefix sum also can be a complex operation. It may be desirable to pipeline the design, or to share adder resources.



But I think we do not have any prefix operatorn on our keyboard; so should we design a model for that purpose?
 

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