Signal Value from Multiple Processes

Q: Why can't we assign a signal value from multiple processes?

i.e. why is this bad?

because you dont know what the output will be.
Imagine proc0 is 0 and proc1 is 1, what should F be?

You can drive a signal from multiple processes if at most one process sets the value to '0', '1' and every other process sets the value to 'Z'. (there is also 'L' and 'H')

FPGAs do not have internal tristates, however the synthesis tools may still be able to infer logic from this structure.

Because of the above requirement, this style is almost never useful when compared to assigning the signal in a single process.

Hi,

imagine two different cars bonded with a rope.

As long as both cars try to pull into the same direction there is no problem.

But if one cars tries to pull to the right, the other car tries to pull to the left.
What will happen?
Maybe one car will lose the fight and will be pulled to the other side. But which side? --> To the side of the stronger car.

***
Which of your two processes is the stronger one?

Klaus

Umm.. according to my little understanding, signals get updated at the end of a process.

So if at end of Proc0 value of F is say 1, then when proc1 runs its can change he value of F to 0 if it wills.

Or is it that processes will run at the same time?! I am confused because we don't have a clock!

The process is entered when the signals in the sensitivity list change. Only if A/B and C/D have inputs that change at the same time will both proc0 and proc1 run in parallel.

If the inputs for A/B change and C/D stay the same then proc0 will be entered and if the result of proc0's AND gate is inverted from the output of proc1 then you'll end up with an X in simulation and a problem with synthesis as you've shorted two outputs together. If the two procs drive their outputs to the same value then the result will be 0 or 1.

If such a thing was done on a physical PCB you would end up burning up one or both parts (AND gate, OR gate) output driver. As VHDL is trying to simulate what can be done in hardware, this is not allowed an will result in X's in simulation and probably an error in most synthesis tools.

You definitely need to keep in mind VHDL is meant to describe hardware.

dzafar said:

Umm.. according to my little understanding, signals get updated at the end of a process.

So if at end of Proc0 value of F is say 1, then when proc1 runs its can change he value of F to 0 if it wills.

Or is it that processes will run at the same time?! I am confused because we don't have a clock!

Click to expand...

Thats thinking like a software engineer.
Think of it like the hardware in the picture - not the code.

Haha.. I know it's very clear from the picture. But I need to get an understanding of the code. The prof is going to ask us questions like "if the code is valid or not and why or why not" in the exam. How can I answer that based on the code?

Ahh!! This makes total sense! Thanks

ads-ee said:

The process is entered when the signals in the sensitivity list change. Only if A/B and C/D have inputs that change at the same time will both proc0 and proc1 run in parallel.

If the inputs for A/B change and C/D stay the same then proc0 will be entered and if the result of proc0's AND gate is inverted from the output of proc1 then you'll end up with an X in simulation and a problem with synthesis as you've shorted two outputs together. If the two procs drive their outputs to the same value then the result will be 0 or 1.

If such a thing was done on a physical PCB you would end up burning up one or both parts (AND gate, OR gate) output driver. As VHDL is trying to simulate what can be done in hardware, this is not allowed an will result in X's in simulation and probably an error in most synthesis tools.

You definitely need to keep in mind VHDL is meant to describe hardware.

Click to expand...

Question: You mentioned that the process is entered when the inputs change. So if A/B change but C/D stay the same, as you say, then proc1 should not run at all. And "if the result of proc0's AND gate is inverted from the output of proc1 then you'll end up with an X" won't happen. Am I correct?

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Is this explanation valid: "When we have two processes running under the same architecture then both of them cannot update the same signal"?

dzafar said:

Question: You mentioned that the process is entered when the inputs change. So if A/B change but C/D stay the same, as you say, then proc1 should not run at all. And "if the result of proc0's AND gate is inverted from the output of proc1 then you'll end up with an X" won't happen. Am I correct?

Click to expand...

No proc1 is assigning that output to the opposite value from proc0 CONTINUOUSLY until changed. You are thinking like a software engineer where assigning a variable occurs at that line of code and any other lines of code that assign something to the same variable don't affect the line of code being executed.

Think hardware...the process is an IC that is driving the output to a value, if you try to drive that IC with another IC to a different logic value then you will have contention and will burn one or both outputs of the two ICs.

Is this explanation valid: "When we have two processes running under the same architecture then both of them cannot update the same signal"?

Click to expand...

If you want to produce a hardware design, then yes. I'm sure there are some mutually exclusive cases where you might be able to abuse VHDL and implement two processes that drive the same signal, but if you insist on coding like that, then IMO you should not go into FPGA/ASIC design and stick with software.

dzafar said:

- - - Updated - - -

Is this explanation valid: "When we have two processes running under the same architecture then both of them cannot update the same signal"?

Click to expand...

No - in some cases you may want to have a signal driven from two processes, like a common bus (usually on a pcb) that is shared by several peripherals. Here, the "inactive" units need to drive "'Z" onto the bus (high impedance) so that the bus master can drive the real data.

Your original example can only be allowed at external connections to an FPGA. It is an error for a signal to be driven from two places inside an FPGA. The language only allows it via a "resolution" function that gets called every time a signal is driven from two (or more) places. This is how your '0' and '1' are "resolved" to an 'X'. Std_logic is the only standard VHDL type that allows it to be driven from multiple processes - any other type (for example, std_ulogic, integer, boolean) would result in a syntax error because you tried to drive it from more than one process. This is why many people now favour std_ulogic rather than std_logic, as driving a signal from signal from multiple places is never done in reality anymore, other than some shared external interaces.

Hi,

Is the following possible?

...
process (A, B, C, D)
begin
end process;
...

In this case, if say both A and C change, then statement 0 will change F (to say, 0) then statement 1 will update/overwrite it to say, 1 and F will be assigned 1 after end process (because signals get updated after 'end process', right?

Thanks

The last assignment reached will be the statement that is used. The a and b statement will never be used. Even if you had f and a and b, it would not matter for signal assignments. The c and d assignment will always be reached before the end of the process.