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[SOLVED] Procedure with sequential process edge detection

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nsgil85

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Hi all

I wrote a simple dff procedure inside package as shown below.....
Code VHDL - [expand]
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procedure dff(signal clock : in std_logic ; signal input_signal : in std_logic ; signal output_signal : out std_logic) is
        begin
            if rising_edge(clock) then
                output_signal <= input_signal;
            end if ;
end procedure dff;



(procedure called from process outside)

Is there any way to "save" signal inside the procedure so i can create simple edge detection (with "not" and "and" operators)

something like this:
Code VHDL - [expand]
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procedure edge_detection(type_of_edge : string ; signal clock : in std_logic ; signal input_signal : in std_logic ; signal output_signal : out std_logic) is
        signal sig_sampled : std_logic ; -- signal NOT ALLOWED 
        begin
            if rising_edge(clock) then
                sig_sampled :=  input_signal;
            end if ;
            if type_of_edge = "pos" then
                output_signal <= (not sig_sampled) and input_signal ;
            elsif type_of_edge = "neg" then 
                output_signal <= (not input_signal) and sig_sampled ;
            end if ;    
    end procedure edge_detection ;


Thanks
Gil
 

Hi,

The DFF now "detects" the edge of "clock".

Do you want to detect the edge of "input_signal"?
What edge? rising, falling, both?

--> two cascaded DFF. both clocked on rising edge of "clock"
input_DFF1= input_signal
input_DFF2 = output_DFF1

rising edge: output_DFF1 AND *output_DFF2

falling edge: *output_DFF1 AND output_DFF2

both: output_DFF1 XOR output_DFF2

Klaus
 

Thanks Kalus

Do you want to detect the edge of "input_signal"?
Click to expand...
YES,

I know to implement it with process (with one DFF), but im trying to understand the syntex for implementation inside a procedure
for example:

Code VHDL - [expand]
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signal  s_input_signal : std_logic ;
begin
process(clock)
    begin
        if rising_edge(clock) then
            s_input_signal  <= input_signal;
        end if;
 end process;
    output_signal    <=    (not s_input_signal  ) and input_signal;     -- rising edge



thanks
Gil
 

Hi,

your solution gives an unsynchronized output. You should avoid this.
Glitches, timing errors, malfunction may occur. --> use a second DFF

Klaus
 

input_DFF1= input_signal
input_DFF2 = output_DFF1
Click to expand...

Ok so what is the syntax for adding signals input_DFF1,input_DFF2 to procedure?
 

I do question why you are trying to do this from a procedure. The procedure must be called from a process anyway, so you're just hiding functionality behind the procedure. While it can work, it does go against convention. Most engineers dont usually use procedures anywhere in RTL code, saving them for testbenches.

Hi,

your solution gives an unsynchronized output. You should avoid this.
Glitches, timing errors, malfunction may occur. --> use a second DFF

Klaus
Click to expand...

If s_input_signal is synchronous on the same clock, there is no glitch.


Ok so what is the syntax for adding signals input_DFF1,input_DFF2 to procedure?
Click to expand...

something like this?

Code VHDL - [expand]
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library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
 
 
entity proc_test is
end entity proc_test;
 
architecture rtl of proc_test is
 
  signal clock          : std_logic := '0';
  signal input_signal   : std_logic;
  signal input_signal_r : std_logic;
  signal input_signal_r2 : std_logic;
  signal rising         : std_logic;
  signal falling        : std_logic;
 
  procedure edge_detection(       type_of_edge    :       string ; 
                           signal clock           : in    std_logic ; 
                           signal input_signal    : in    std_logic ; 
                           signal input_signal_r  : inout std_logic ;
                           signal output_signal   : out   std_logic  ) is  
  begin
    if rising_edge(clock) then
        input_signal_r <=  input_signal;
        
        if type_of_edge = "pos" then
          output_signal <= (not input_signal_r) and input_signal ;
        elsif type_of_edge = "neg" then 
          output_signal <= (not input_signal) and input_signal_r ;
        end if ;    
        
    end if ;
    
  end procedure edge_detection ;
  
begin
 
 
  clock <= not clock after 5 ns;
  
  input_signal <= '0', '1' after 33 ns, '0' after 56 ns;
  
 
  edge_detection("pos", clock, input_signal, input_signal_r, rising);
  edge_detection("neg", clock, input_signal, input_signal_r2, falling);  -- use R2 as you could cause multiple driver error
 
end architecture;
 

I do question why you are trying to do this from a procedure. The procedure must be called from a process anyway, so you're just hiding functionality behind the procedure
Click to expand...

Correct!, The idea is to minimize code lines(it is repetitive process in my code), & arranging with packages/libraries

about the code proposal, my question is how would you write it inside a package with a procedure (not in process which i've done already)
procedure will not accept signals, only variables

Thanks
Gil
 

nsgil85 said:
Correct!, The idea is to minimize code lines(it is repetitive process in my code), & arranging with packages/libraries

about the code proposal, my question is how would you write it inside a package with a procedure (not in process which i've done already)
procedure will not accept signals, only variables

Thanks
Gil
Click to expand...

You can literally copy, paste my procedure into a package and it will work the same.
You can have signals in a package, but you probably cannot synthesise them (quartus wont).
else you need local signals to store values. Values cannot be stored between procedure calls inside the procedure itself.
 
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