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DRC errors reported by Synopsys Hercules

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bhaismachine

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Hello,

I have recently started using IC Compiler and Hercules tools from Synopsys. I am using them for automatic place and route of gate level netlist generated using Synopsys 90nm standard cell library. When I tried to run DRC on the GDS file created using IC Compiler I received following design rule violations. I am tried to looked up about these errors and did some reading but I think it would better if I can discuss this with someone on here.

Would anyone please help me understand meaning of these DRC violations and more important a way to fix this on IC compiler? The layout was generated automatically using script. If necessary I can upload the relevant section of my script here. Thanks!

Code:
ERROR SUMMARY

NWELL.S.1: NWELL minimum spacing between wells at same potential 0.65um
 EXTERNAL nwell { } (163) ............................... 2 violations found.

PIMP.S.1: Minimum space=0.24um 
 EXTERNAL pimp { } (163) ................................ 2 violations found.

NIMP.S.1: Minimum space=0.24um 
 EXTERNAL nimp { } (163) ................................ 3 violations found.

M1.DN.1  M1 density must be < 60% in whole chip, calculated by 100umx100um step 50um
 DENSITY m1 { } (163) ................................... 30 violations found.

M1.DN.2  M1 local density must be < 90% range over 20umx20um step 10um
 DENSITY m1 { } (163) ................................... 899 violations found.

M2.DN.1  M2 density must be < 70% in whole chip, calculated by 100umx100um step 50um
 DENSITY m2 { } (163) ................................... 36 violations found.

M2.DN.2  M2 local density must be < 90% range over 20umx20um step 10um
 DENSITY m2 { } (163) ................................... 961 violations found.

M3.DN.1  M3 density must be < 70% in whole chip, calculated by 100umx100um step 50um
 DENSITY m3 { } (163) ................................... 36 violations found.

M3.DN.2  M3 local density must be < 90% range over 20umx20um step 10um
 DENSITY m3 { } (163) ................................... 961 violations found.

M4.DN.1  M4 density must be < 70% in whole chip, calculated by 100umx100um step 50um
 DENSITY m4 { } (163) ................................... 30 violations found.

M4.DN.2  M4 local density must be < 90% range over 20umx20um step 10um
 DENSITY m4 { } (163) ................................... 899 violations found.

M5.DN.1  M5 density must be < 70% in whole chip, calculated by 100umx100um step 50um
 DENSITY m5 { } (163) ................................... 36 violations found.

M5.DN.2  M5 local density must be < 90% range over 20umx20um step 10um
 DENSITY m5 { } (163) ................................... 961 violations found.

M6.DN.1  M6 density must be < 70% in whole chip, calculated by 100umx100um step 50um
 DENSITY m6 { } (163) ................................... 36 violations found.

M6.DN.2  M6 local density must be < 90% range over 20umx20um step 10um
 DENSITY m6 { } (163) ................................... 961 violations found.
 

density errors: it means you didn't do metal fill. check with PDK. this is trivial.
nwell errors: you are doing something wrong. you either forgot to add filler cells for well continuity, or you have mixed cells with different wells. check layout, mistake should be easy to spot.
 
density errors: it means you didn't do metal fill. check with PDK. this is trivial.
nwell errors: you are doing something wrong. you either forgot to add filler cells for well continuity, or you have mixed cells with different wells. check layout, mistake should be easy to spot.

Hello ThisIsNotSam,

Thanks for your response. I tried inserting filler cells with the following command and it got rid of all the nwell errors though the previous metal density violations still show up. Isn't the command below supposed to do a metal fill ?

Code:
insert_stdcell_filler \
-cell_with_metal "SHFILL1 SHFILL2 SHFILL3" \
-connect_to_power "VDD" -connect_to_ground "VSS"

Thanks!
 

Hello ThisIsNotSam,

Thanks for your response. I tried inserting filler cells with the following command and it got rid of all the nwell errors though the previous metal density violations still show up. Isn't the command below supposed to do a metal fill ?

Code:
insert_stdcell_filler \
-cell_with_metal "SHFILL1 SHFILL2 SHFILL3" \
-connect_to_power "VDD" -connect_to_ground "VSS"

Thanks!

Nope. Filler cells are one thing, metal fill is another thing. Refer to the PDK for how metal fill should be done and what densities have to be observed.
 
Nope. Filler cells are one thing, metal fill is another thing. Refer to the PDK for how metal fill should be done and what densities have to be observed.

Hello ThisIsNotSam,

Thanks again for answering and for the explanation. This is my first attempt at layout design (since I mostly work with RTL design). I referred to the design kit documentation regarding design rules and found this table regarding metal densities. So I understand the minimum and maximum limits of metal densities, though I am not sure about how to fix them. Since the placement and routing was done automatically, I am trying to figure out the steps (or IC compiler related commands) to fix these violations with metal fill.

I am going to play around with different options related to metal fill on IC compiler (and also go through it's documentation) and see if I can get rid of those.

Screenshot from 2017-02-16 14-31-47.png
 

Nope. Filler cells are one thing, metal fill is another thing. Refer to the PDK for how metal fill should be done and what densities have to be observed.

Hello ThisIsNotSam,

I went through the IC Compiler user guide and made some changes to my script and added commands for metal fill. I have added part of this script below, which is responsible for filling. I still get those metal density DRC violations when checked with Hercules.

Code:
#insert_stdcell_filler
save_mw_cel

set_physical_signoff_options -exec_cmd {hercules} \
  -drc_runset {../hercules/DRC/rules.drc.9m_saed90_hercules.ev} \
  -fill_runset {../hercules/DRC/rules.fill.9m_saed90.ev}

insert_stdcell_filler \
  -cell_with_metal "SHFILL1 SHFILL2 SHFILL3" \
  -connect_to_power "VDD" -connect_to_ground "VSS"

signoff_metal_fill

route_opt -incremental -size_only

What am I missing ? Thanks !
 

I believe the command is insert_metal_fill, but I am not proficient in ICCompiler

Hi ThisIsNotSam,

So I have been playing around with different configurations of the insert_metal_filler command since yesterday. Unfortunately still couldn't get rid of those metal density errors. Also the command that I mentioned in my previous post (sign_off_metal_fill) wouldn't work either because apparently ICC cannot find Hercules path, even though I can run hercules from bash prompt. I might have to figure that out though.

Anyway, when I try to run the insert_metal_filler command I get the following warning (and there seems to be no metal filling done):

Code:
WARNING: Fill layer range must be within Min/Max Routing Layer (2, 4)


So I tired running the insert_metal_filler command with the following options to see if fixing that warning would help

Code:
insert_metal_filler  -out self -floating_via_ftr_spacing  -from_metal 2  -to_metal 4

The previous command makes the layout look like this:

Screenshot from 2017-02-17 04-32-11.png

I believe it should look like the one in the picture above. Running DRC on this layout gave the same metal density errors. Maybe I am missing something very obvious, unfortunately I haven't had any luck figuring it out.

Thanks for your continued help. I really appreciate it.
 

Read the documentation for the command. There must be another command that you have to use in conjunction with insert_metal_fill. You have to be able to tell the tool what goal density you want, somewhere, somehow. My guess is the metal fill process is not working because you didn't set a goal.
 
Read the documentation for the command. There must be another command that you have to use in conjunction with insert_metal_fill. You have to be able to tell the tool what goal density you want, somewhere, somehow. My guess is the metal fill process is not working because you didn't set a goal.

Hello ThisIsNotSam

signoff_metal_fill : I read through the document and the only thing that I believe is related to the metal density goal is the signoff_metal_fill command. This is because prior to running this command, according to the documentation, I have to setup physical signoff options which include providing DRC rules runset and metal fill runset from the foundry along with the layer mapping file and the name/path of the DRC checker executable (hercules in this context). Here is the screenshot of this command's different options. I thought the GUI screenshot would be easier than pasting the man output for this command.

Screenshot from 2017-02-17 16-15-20.png


Even though I can run this command, I don't think it's working. One thing to note is that it doesn't do metal fill in the current CEL view but does it in the FILL view. So I am not sure if anything special should be done while streaming out the gds file after this is done.

insert_metal_filler
: This is the other command that is for metal filling. I have tried this one and described what the results looked like in my previous comment (I made a typo after the layout's screenshot in my previous post. I wanted to say that, 'I don't think the layout should look like this'). Here is the screenshot of this command's different available options.

Screenshot from 2017-02-17 15-40-20.png

I am not sure what I am missing at this point. Once again, thank you for the taking the time to reply.
 

I can tell you that you want the second command. the signoff version takes timing into account, and that is just one more thing to screw you. go with insert_metal_filler. there must be a way to set the density goals somewhere. there must a related command or something.
 
Here The violation is due to Maximum metal Density. The violations shows that the density must be less than some % with respective density window. [Correct Me if I am wrong]. You might want to have a closer look at the density of a metal in particular area/.

In your Tech File, you might have density related syntax. Compare those with the foundry specific drc deck
 

normally foundry provides you a drc rule instruction doc that helps you understand what those rules are。check it may faciliate you fix these violations. nwell minimum spacing (i.e. implant layer spacing requirement in Tech LEF) violation typically results from inserting the wrong type of filler cells, for example insert a SVT Filler1 between two HVT cells; there should be some options that can check this when inserting fillers(in Cadence innovus there are such command, not quite familiar with ICC) and make sure you use the approriate filler types。(HVT SVT LVT)。
 

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