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what are the options available to increase the operating frequency of a digital design?

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anilineda

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Hello all,


Is there any way of increasing the rated speed of the design , otherthan modifying the code.
i thought of physical constriants to constraint routing paths in fpga fabric which will alter the longer paths to smaller ones and hence increases the operating speed . (educate me, if im wrong anywhere)

so,can i do something with timing constraints to UP the operating frequency without violating the paths .? if yes, what are those and give me the reference to know more.

regards,
Anil
 
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first, if you are asking about FPGAs, this is the wrong subforum.

you can tweak the constraints all you want, but assuming you will do a better job than the tools for a large sized design is not realistic. there is no magic knob you can play with and get more speed out of a design.
 

@anilineda,

You can try to adjust the timing constraints. This might work if the design can meet them. You can also try enabling various optimizations which could allow a tradeoff between area and performance.

This might not work and timing might not be met. At that point, you would need to look into architectural or device changes.
 

If your design can't meet timing constraints, and you've tried different optimizations (as suggested) then you are probably going to have to change your design. You could also try manually floorplanning, but I've never had any great improvements doing that.
Your timing report should tell you where your problems are.
Also, look at false/multi cycle paths. You might be able to get some relief there.
 

barry said:
You could also try manually floorplanning, but I've never had any great improvements doing that.
Click to expand...
I wouldn't look at manual floorplanning as as improving timing but making your timing more consistent from run to run on paths that should always make timing but for some reason the placement is inconsistent and results in timing problems. This is something that used to happen a lot in ISE for DDR interfaces on older parts like Spartan 3 and the V4.

Also both ISE and Quartus have register retiming, which can be enabled that can move FFs around to balance the logic between FFs. This is not available in Vivado AFAIK (I haven't installed any of the 2016.x versions).
 

So basically you want more performance without changing
anything but the constraints? How heroic.

Do you even know what your timing bind really is?

Maybe it's something simple like too much combo logic
depth between registers. But to fix that you might have
to (oh, noes!) touch the design.
 

If you expect your design to meet timing (or functionality or utilization or...) without any modifications, perhaps you've chosen the wrong career path.
 

barry said:
If you expect your design to meet timing (or functionality or utilization or...) without any modifications, perhaps you've chosen the wrong career path.
Click to expand...


perhaps that you have not read my question properly.
 

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