[SOLVED] Draw RAM memory diagram

Draw a block diagram of 32kX8 bit RAM memory using memory components 8kX8 bit and decoders DEC 3/8.

32kX8 b=32000Bytes
8kX8 b=8000Bytes
Total number of memory components is n=(32KX8)/(8KX8)=4.

How to determine the number of address lines of one memory component?
In the case where the number can be represented as the power of two (2^x), x would be the number of address lines of memory component capacity (here we have 8k which is not the power of two).

Total number of decoders should be 1+4=5.

There are total 32 decoder connectors, and 4 memory components.
I don't understand how to connect connectors of decoders to memory components.
How many connections are needed and how to determine connections?

Here is my diagram without decoders - memory components connections (see attachment3).
Here is my diagram with decoders - memory components connections (see attachment2).

Here is an example of 128KX8 b RAM (this is Kibibit) memory using memory components 8KX8 b and decoders DEC 3/8 (see attachment1).
Here we have 16 memory components and 13 address lines for each component (because 8K can be express as the power of two - 2^13=8K ). Here, each connector of every decoder is connected to one select line of each memory component (there are total 16 connectors and 16 memory components).

In the original question, there are total 32 decoder connectors, and 4 memory components.

Question: What should be the correct diagram for the original problem (how to determine the connections), and how to determine the number of address lines of memory component when capacity is not the power of two?

Note: This is not a homework - I am practicing for exam.

Hi,

32k = 32 x 1024 = 32768 = 2^15 = 15 address lines
8k = 8 x 1024 = 8129 = 2 ^13 = 13 address lines.

connect A0 ... A12 directely from addressbus to RAM (edited for better understanding)
Feed A13, A14 to the decoder
4 lines output of the decoder go to the four CS of the 4 8k RAMs

Klaus

KlausST said:

32k = 32 x 1024 = 32768 = 2^15 = 15 address lines
8k = 8 x 1024 = 8129 = 2 ^13 = 13 address lines.

Click to expand...

k is not prefix Kibi. Shouldn't it be 32k=32 x 1000?

Could you draw a sketch using my attachment2?

- - - Updated - - -

Your description tells that we only use one decoder. Why?

Hi,

k is not prefix Kibi. Shouldn't it be 32k=32 x 1000?

Click to expand...

I admit it isn´t obvious.
But in every standard RAMs datasheet "1k" means 1024.
If you´re curious you could just open a couple of RAM datasheets.

Klaus

If we would have k as kilo instead of Kibi, what would be the number of address lines?

Hi,

I corrected my post#2 regarding address wiring. I removed the obsolete questions, not to confuse others. I hope you don´t mind.

***
Drawing sketch: no, (no time)

One decoder: Why more?
Two address inputs (A13, A14) and CS --> four outputs (CS0 ... CS3) is all you need.

Kibi: 1000 simply makes no sense. We think binary.

Klaus

KlausST said:

Two address inputs (A13, A14) and CS --> four outputs (CS0 ... CS3) is all you need.

Click to expand...

It is strange to me why we don't use 4 additional decoder because I have an example of 512x1b with 3/8 decoders and 16x1b memory components were 1+4 decoders and 3 memory components are used.
Why we have 4 additional decoders here?

Hi,

Each RAM IC needs an independent CS signal.
If you have 4 RAMs and one docoder generates 4 CS signal, then everything is fine.

If you have more RAMs you need more CS signals,
If you have decoders that generate 4 signals only, then you need to cascade decoders.

Klaus

1024 is because it is a power of 2. As binary numbers double in size each time you add a bit, the progression is 1, 2, 4, 8, 16, 32, 64, 128, 256, 512, 1024, 2014, 4096, 8192. That means you can select all the addresses up to 8192 using 12 bits, if you used decimal 1000 as size multiple, you would not be able to reach all the addresses without adding extra address lines which would be inefficient.

You mentioned using a "Dec 3/8" which I assume to be a 3 input to 8 output decoder (like a 74LS138). What you do is address all the 4 memories in parallel with A0-A12 but only select one of the 8K devices at a time. You select only one by using the decoder outputs, lets say Y0, Y1, Y2 and Y3 with those going to the CS (Chip Select) pin on each of the four 8K devices. That means that although your addresses go to all the memories at the same time, only the one activated with the 'Y' signal will respond. Now if you connect and additional TWO address lines to the input of the decoder, these effectively become A13 and A14. By using those two extra lines you select the first, second, third or fourth 8K block giving you 32K in total.

Note I mentioned TWO additional address line to the decoder, you must keep the third input (most significant bit) at logic low level. If you make it high, the decoder outputs Y4, Y5, Y6 and Y7 will be active but they don't connect to any memory CS pin so nothing wil be selected. However, you could use it to select another 4 8K memories to give 64K in total.

Note: when we refer to memories as being 8kX8 it means 8k (8192) addresses, each address holding 8 bits. You don't decode the 8 bits, they are the storage size of the address. Each address holds 00000000 to 11111111 as individual bits.

Brian.