Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

HOW to improve the power rejection ratio of BGR?

Status
Not open for further replies.

ice

Newbie level 3
Joined
Mar 5, 2005
Messages
4
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
1,305
I want to design a CMOS Bandgap Reference Circuit.
HOW to improve the power rejection ratio of BGR?
 

Depends on what architecture u are using.
1.IF simple cascode current mirror, then incre4se the lengths of the transistors (PMOS).
2. You could have a pre-regulated supply for your BGR.
3. If u have an amplifier that is maintaning the the voltage across the BJT and BJT plus resistor in PTAT core. Ansd output of it is driving the gate of PMOS current source, then your opamp must pass the complete supply ripple to the gate of the PMOS where the supply ripple would become a common mode signal.
Opamp with diode load connected to VDD would be the architecture choice
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top